FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6376 Discussions

simulate user issued refresh to emif ip in agilex

CosmoKramer
Employee
372 Views

I would like to modify emif simulation model to use user refreshes as well. right now, even though i selected this option in the ip editor, i do not see it in the generated example design. 

 

do you have a simulation design with user defined refreshes? if not, which files should I change to insert the refresh commands at regular intervals?

My goal to see how read/write operations are affected by user issued refresh commands. 

 

External Memory Interfaces Intel®
Agilex™ FPGA IP User Guide
Updated for Intel® Quartus® Prime Design Suite: 21.4
IP Version: 2.6.0

0 Kudos
2 Replies
AdzimZM_Intel
Employee
340 Views

Hi Sandy,

 

The EMIF example design do not control the MMR interface to perform user refresh.

So user needs to add the user refresh control logic into the simulation to perform the user refresh.

 

Please refer to register in picture below to issue a user refresh request.

fresf.png

 

Regards,

Adzim

0 Kudos
AdzimZM_Intel
Employee
283 Views

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


0 Kudos
Reply