timing_error_for_pll_afi_clock_on_ddr3_ip_controller

[SERMASWATHIKA]

Hi Team,

  I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setting) and uses afi_clock(200 Mhz) to connect the clock of other interfaces.

pll_clock of ddr interface is 50 Mhz. connected from the osciallator in the board.

 Nios processor also connected with afi clock only (200 Mhz)

For this design , i am getting pll_afi_clock setup time violation.

i have attached the timing report. 

PLease give solution for this.

[TingJiangT_Intel]

Hi there, I can't open timing analyzer with the project you provide, please make sure the timing path can be showed in timing analyzer after you archive the project.

Thanks a lot.

[SERMASWATHIKA]

Hi ,

  I have added the compiled project archive here. i have archived the project in 22.1 . Please compile the project after restoration. then you can open the timing analyser. i have checked in my pc..

[TingJiangT_Intel]

Hi there, you are using 22,1 std right? I can't start the compilation with your project. It always exit unexpeactly.

[TingJiangT_Intel]

Here is the error.

BTW I notice that your qsf shows that you used 21.1 pro. May I know the exact edition you are using to open the project.

[SERMASWATHIKA]

Hi,

I am using quartus 22.1 version only. And this is the qsf file which i am seeing in my archive folder. I am not sure how this is changing in your tool

[TingJiangT_Intel]

Hi there, I download your project again. now the qsf of the restored project is the same with what you showed. However I still can't start the compilation process with the same issue.

Can the archived project start compilation process from your side?

[SERMASWATHIKA]

yes, i have compiled the restored archive project , after that only i have shared to you

[TingJiangT_Intel]

BTW, you can select the following option when archive the compiled project. With these files we can directly open the timing analyzer, and please check if it can show the paths in timing analyzer after archived.

[SERMASWATHIKA]

Hi,

Now i have created the project archive with the options which you have mentioned in the previous message. with version incompatible database file, qar size is exceeded the maximum limit. So i have added qar which has report files alone.

[TingJiangT_Intel]

It's weird, I failed to restore your project with 22.1 standard edition:

[TingJiangT_Intel]

Since I can't open your project, please help check following questions:

1, Please check if the launch clock and latch of the violation path are the same clock.

2, Please check the ignored constraint report to make sure all constraints are available.

[SERMASWATHIKA]

Hi,

I have checked the launch and latch clock, both are same.

i didnt get the 2nd point you mentioned regarding ignored constraint path.

[TingJiangT_Intel]

For the 2nd point, there is a report in timing analyzer which shows if there any constraints are ignored.

Check this to make sure if all your constraints are valid.

[TingJiangT_Intel]

The option is in the task window as following:

[SERMASWATHIKA]

Hi,

no constraints were ignored

[TingJiangT_Intel]

I see. All the violation path are related to which IP? What about the logic level of these violation paths.

[SERMASWATHIKA]

all violations are from ddr3 ip files. all are related to pll_afi_clock signal

[TingJiangT_Intel]

In addition, is there any warning message in the timing analyzer?

[SERMASWATHIKA]

No,There is no warnings in timing analyser

[TingJiangT_Intel]

Hi there, I checked your project please pay attention to the following critical path

[TingJiangT_Intel]

This data path is too long, and its logic level is high:

You created a loop here which has increased the data delay, please consider inserting pipeline registers into this path in your design to reduce the logic level.