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[AnandRaj_S_Intel]

Hi,

Can you share more information on Development kit and tool version & edition used?

1. After analysis and synthesis , have you done with pin assignments ?
2. After pin assignment run full compilation. which will generate .sof file under project directory or output_files under project directory.
3. Now need to do the hardware setup, Check MSEL jumpers (JTAG-based configuration takes precedence), Connect the USB BLASTER to on board JTAG header or on-board usn-blaster USB.and power up the board
4. From Quartus go to tools->programmer->hardware setup->Select USB blaster.Click mode->JTAG, Click on Auto detect see if you can see the fpga device.
5. Now you can add the .sof file and program by clicking on start.

Refer below link

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/tt/tt_my_first_fpga.pdf

Regards

Anand

[hdjdcmv]

Dear Anand,

Thank you for giving me answer.

1.It already pin assigned and it has created .sof file which i will add during JTAG.Please see the attachment.

2.USB Blaster I already ordered.It is on the way.Hopefully,It will work.

3.Basically,I want to run the exiting code with CAN and see the result.Then i should replaced by CAN FD in CAN.I have more work with VHDL Code.I need to make them fit (IFI CAN FD) with existing implementation.

4.Can you tell me what is QSYS tool ? I have seen few tutorial.Some design starts with QSYS and some other is normal way(write code,compile,JTAG). can you tell me the difference ?

Thank You.

Rajat

[AnandRaj_S_Intel]

​Hi Rajat,

Qsys/Platform Designer is a system integration tool, We can use already build and tested IP's from IP catalog or design our own IP's from scratch. By using those IP's and integrating them we can develop a complex system using Qsys.

Simply used for integration of IP's.

For example

1. lets say we want to control an led using a dip switch.                                                                                                                                                                                    Which can be written in simple HDL(VHDL/VERILOG) code. Another way to implement is by using IP's(PIO from Qsys catalog).
2. Complex design will have many interfaces (storage and communication interface) which requires controllers(And which is provided by the IP from catalog)  for communication between them and user logic. Which may include many IP's.                                                                                                                       

If we integrate in with HDL we may face many integration issues which can be eliminated by QSYS/Platform Designer.

kindly refer below links.

https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-prime/features/qts-platform-designer.html

https://www.intel.com/content/www/us/en/programmable/support/training/course/oqsys1000.html

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/qsys/exm-qsys-tut.html

Regards

Anand

[hdjdcmv]

Thank You for your reply.

I have a IFI CAN-FD IP-core installer.How could i install this and how could i correlated existing CAN with CANFD IP Core ?

I am getting this response.I can not install this.

Can you help me regarding this issue.

Thank you.

Rajat Barmon