FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5890 Discussions

what is debug_mem_slave interface of Nios II Processor

VVavr1
Beginner
1,390 Views

I have noticed debug_mem_slave Avalon-MM slave interface in Nios II Processor IP core but I am not able to find any documentation what it does?

 

I assumed it is some kind of on-chip ram embedded in Nios II but I am not able to generate BSP without on-chip ram.

 

SEVERE: CPU "nios2_gen2_0" has no memories connected to its Avalon master(s)

 

So it seems that debug_mem_slave is not substitute for on-chip ram.

0 Kudos
1 Reply
Ahmed_H_Intel1
Employee
516 Views
Hi, This is useful in debugging, please read "Nios II Gen 2 Processor Reference Guide"> Break Exceptions https://www.intel.com/content/www/us/en/programmable/documentation/iga1420498949526.html#iga14093355... For example, if you want to set the break point when Debugging Nios II, but at this time you can not get the values of various registers from JTAG unless you skip the instruction to another memory. For this reason, it is necessary to skip to separate memory at Break, and it is automatically set to debug_mem_slave when using JTAG debug module. Embedded_guy
Reply