FPGA, SoC, And CPLD Boards And Kits
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A pulse occurs during MAX 10 update while power is on

JW1121
Novice
245 Views

Hi,

While MAX10 FPGA is programmed during power on state I find a  low pulse(~ns) (occurs for each output pin.

Does anybody know how to fix this issue.

 

 

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1 Reply
ShafiqY_Intel
Employee
216 Views

Hi JW1121,

 

Have you tried to set the unused pins to tri-stated in Quartus?

Please refer to the following picture (go to Assignment --> Device..)

Screenshot (300).png

 

Regards,

Matt

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