In the Arria 10 GX FPGA Development Kit. LVDS clock signals are provided to the REFCLK_GXB pins. The clock signals are AC coupled as per the pin connection guide . (Only HCSL can be DC Coupled)
However in the schematics I am unable to see any external termination required for AC- coupled circuit to set the VICM midpoint . Does the FPGA take care of it internally .If so what is the VICM it sets .
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