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ARRIA 10 - REFCLK pins

vivekt
Beginner
227 Views

In the Arria 10 GX FPGA Development Kit. LVDS clock signals are provided to the REFCLK_GXB pins. The clock signals are  AC coupled as per the  pin connection guide . (Only HCSL can be DC Coupled)

However in the schematics I am unable to see any external termination required for AC- coupled circuit  to set the VICM midpoint . Does the FPGA take care of it internally .If so what is the VICM it sets . 

 

 

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2 Replies
EngWei_O_Intel
Employee
199 Views

Hi Vivek

You need to enable the OCT in your FPGA design for REFCLK_DP_P/N. The OCT will take care of the Vicm.

 

Thanks.

Eng Wei

EngWei_O_Intel
Employee
154 Views

Hi Vivek

We do not receive any response from you to the previous answer that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Eng Wei

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