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Beginner
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ARRIA 10 - REFCLK pins

In the Arria 10 GX FPGA Development Kit. LVDS clock signals are provided to the REFCLK_GXB pins. The clock signals are  AC coupled as per the  pin connection guide . (Only HCSL can be DC Coupled)

However in the schematics I am unable to see any external termination required for AC- coupled circuit  to set the VICM midpoint . Does the FPGA take care of it internally .If so what is the VICM it sets . 

 

 

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Employee
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Hi Vivek

You need to enable the OCT in your FPGA design for REFCLK_DP_P/N. The OCT will take care of the Vicm.

 

Thanks.

Eng Wei

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