ARRIA10 GX Devices Secure JTAG configuration

[bkanal]

Can we use Tamper Protection Mode and Configuration Readback options in Arria10 GX devices.

Is there anyone who implement this issue?

Can we use these design security options only SoC series of FPGA?

Thank you

[NurAiman_M_Intel]

Hi,

You can refer below in how to set tamper bit:

https://www.intel.com/content/www/us/en/docs/programmable/683269/current/steps-to-enable-tamper-protection-bit.html

Also, configuration readback cannot be used with Arria 10.

Regards,

Aiman

[bkanal]

Thanks NurAiman.

I understand your advice. I am wondering can we use Arria10 GX series for tamper protection. Can we use all Arria10 series for this property or we can use only S series of Arria10.

[NurAiman_M_Intel]

Hi,

Yes, it works on all Arria 10 device.

Regards,

Aiman

[NurAiman_M_Intel]

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

[bkanal]

Thanks NurAiman.

We want to use pure FPGA ARRIA 10 option. We need secure key and authentification options.  

I want to ask you is there any documentation for pure FPGA(ARRIA 10,CYCLONE V, etc.) devices security features except for AN556?