Hi,
We are trying to program an Agilex 3 device over the AVST8 interface, implemented through a CPU using SPI and bit-banging.
Setup (see picture below):
Data is shifted into a serial-to-parallel converter via SPI.
AVST_CLK is generated from the SPI CS signal.
AVST_VALID and AVST_READY are controlled by GPIOs.
With this setup, we can mimic the passive serial programming approach used on Arria FPGAs.
What works:
Programming and testing over JTAG works fine.
The FPGA design itself runs correctly.
What does not work:
During AVST8 programming, AVST_READY goes low after ~8210 bytes and never returns high.
Programming sequence we follow:
CPU initializes pins: nCONFIG=0, AVST_VALID=0
CPU sets nCONFIG=1
FPGA pulls nSTATUS=0
CPU sets nCONFIG=0
FPGA sets nSTATUS=1
CPU provides some clock cycles (~81 cycles) on AVST_CLK (since AVST_READY is low)
FPGA sets AVST_READY=1
CPU sets AVST_VALID=1 and streams configuration data
After 8210 cycles, FPGA sets AVST_READY=0
CPU sets AVST_VALID=0 and continues clocking
At this point, AVST_READY never goes high again.
What we observed:
If we deliberately corrupt the configuration data, nSTATUS goes low after a few cycles — as expected.
This suggests that the FPGA is checking data integrity, but something prevents AVST_READY from recovering.
Our bit-banged AVST_CLK frequency is only about 60 kHz. Could this low frequency be the root cause?
Question:
Why does AVST_READY stay low after 8210 bytes? Is the slow clock (60 kHz) causing the issue, or are we missing something in the programming sequence?
Thanks in advance for your support!
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