Agilex 5 - PCIe

[robertzab]

I have a Devkit - MK-A5E065BB32AES1.

I downloaded the examples from the following link:
https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/a5e065b-modular.html

I ran the pcie_ed project and opened Platform Designer to generate the code. During this process, I get the following error:

Error: pcie_ed_pcie_gts_0: set_instance_parameter_value: No parameter sm_hssi_pcie_ctl_x4_ecrc_strip_hwtcl

I didn’t change anything in the project.

I also created a new project and added the “GTS AXI Streaming Intel FPGA IP for PCI Express” IP core, and I’m getting the same error there as well.

How can I fix this, and what does this error refer to?

Quartus - 24.3.1

[Wincent_Altera]

Hi Robert,

I try to download the from the same link as yours and run full compilation in Quartus v24.3.1.

the compilation PASS 100 % without any error.

Another method you may try is to generate from our IP catalog, you may refer the step in 2.2. Generating the Design Example

• I try to compile the same in IP catalog, the result was passing as well, attach the design .qar file as per your reference purpose
• 
• 

Regards,
Wincent_Altera

[robertzab]

Hi,

Thanks a lot for the info and help. It turned out the issue was on Quartus’ or Windows’ side – I solved the problem last night.

Specifically, on a clean Windows installation, I installed Quartus 24.3.1, and synthesis completed successfully without any errors. So I started looking for the issue on my PC.

Since we have different projects, we also use different versions of Quartus, namely 13.0, 18.1, 21, 22, and the latest 24. I checked the Windows PATH, and it pointed to the newest version.

However, I began removing older versions from the system one by one, and only after removing version 21 did the synthesis finally go through correctly in version 24.3.1.

Apparently, some references were assigned to a path they shouldn’t have been.

The main thing is that the problem is solved. Thanks again for your help!

[robertzab]

Hi,

Thank you for your response.

I downloaded your project and ran it on my device.

I connected the Dev-Kit to the motherboard, uploaded the program, but unfortunately, Windows does not detect any device – the same issue occurs on Linux, no device is detected.

I also have a devkit from Arrow (Arrow AXE5-Eagle FPGA Dev Kit). Using the same project – only changing the pin assignments – Windows detected the connected device, and so did Linux.

According to the documentation (GTS AXI Streaming Intel® FPGA IP for PCI Express Design Example User Guide), I installed the driver:

 

I ran the test program: ./software/user/example – and got the following results:

 

Even when performing individual read and write operations, the result is the same.

From the Ubuntu side, I checked:

robert@robert-Z590:~$ lspci -d 1172:
02:00.0 Unassigned class [ff00]: Altera Corporation Device 0000 (rev 01)

LnkCap:	Port #1, Speed 8GT/s, Width x4, ASPM L0s L1, Exit Latency L0s unlimited, L1 unlimited
		ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
		
LnkSta:	Speed 8GT/s (ok), Width x4 (ok)
		TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-

 

So the link between the device and the computer exists – but there is still a problem with reading and writing.

I checked the signal assignments according to the documentation (GTS AXI Streaming Intel® FPGA IP for PCI Express User Guide) – all pins match the values from the table.

 

I enabled the debug toolkit and got the following results:

Do you have any idea where the issue or error might be? 

[Wincent_Altera]

Hi Robert, 

It seen unusual to me that from your lspci command, it seen like the speed and width is in expected way.
However, the debug toolkit show it stuck at recovery_rcvrlock.. Is this happen during the transition or before the transition ?
Can you please try to redo the equalization ?

I suggest to capture a signalTAP to have a better view.
https://community.intel.com/t5/FPGA-Intellectual-Property/How-to-run-PCIe-Gen-5-Design-Example-using-Altera-FPGA-device/td-p/1640988

Perhaps, you can try to refer the document under Appendix C, D and E. (in case you missing any step)
Although it is targeted Agilex 7 but overall step will be the same.

Regards,
Wincent_Altera

[robertzab]

Thank you for your response.

I’ve reviewed the documents and followed everything according to the documentation.
As I mentioned in my previous message – the system sees the device and has theoretically negotiated the link. Below is also a screenshot from SignalTap:

 

I'm also including the "Event Counter" tab from the console:

 

To be honest, I’m not sure where the issue is.

[Wincent_Altera]

Hi Robert,

I am trying to use the same design and plug in to my Agilex5 Modular devkit.
See if I am able to replicate your issue or not, I might take sometime as my devkit been occupied by other person for some urgent issue.
Will get back to you within 3-5 days.

Meanwhile,

1. is it possible to try in another host ? see if the issue is following or not, so that we can narrow down either is fpga issue or host issue.
2. Do you configure your Host setting ? normally the host setting by default will be "AUTO" for PCIe sides
   I ever experience certain type of host is unable to direct negotiated the speed which causing link up problem.
   Please try to set into your desired speed based on design instead of using "Auto"
   

Regards,
Wincent_Altera

[Wincent_Altera]

Hi Robert,

I try to replicate in the same design that provided to you.
the link up was success, and I do not found any unusual issue.

1. is it possible to try in another host ? see if the issue is following or not, so that we can narrow down either is fpga issue or host issue.
2. Do you configure your Host setting ? normally the host setting by default will be "AUTO" for PCIe sides
   I ever experience certain type of host is unable to direct negotiated the speed which causing link up problem.
   Please try to set into your desired speed based on design instead of using "Auto"

Regards,
Wincent_Altera

[robertzab]

Hi,

When I initially saw in your documentation that there was information about changing the BIOS setting from “AUTO” to the appropriate standard, I changed it immediately, but unfortunately I got the same error.

Unfortunately, I’ve had a problem with the DevKit (MK-A5E065BB32AES1) right from the start—I even started a thread on the forum about it:

https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Problem-DevKit-Agilex-5-MK-A5E065BB32AES1/m-p/1675889#M29564

And from the Arrow distributor, I received their startup kit:

https://www.arrow.com/en/research-and-events/articles/new-intel-arrow-axe5-eagle-fpga-dev-kit-discover-the-molex-interconnects

I’m currently working on that one.

I’ll try to check it on a different host as well. By the way, do you have any Windows drivers?

[Wincent_Altera]

Hi Robert,

Sorry, I miss out your reply in 1Apr, If linux, we do have BUT, not in window version ..

• 2.7. Installing the Linux Kernel Driver

Perhaps you can try to install both window and Linux at the same place (that is what I try in the when drafting the document)

Another things you could try is, try to toggle all Hardware DIP switch back to its default position, this help most of the time to link up (based on my experience)

Regards,
Wincent_Altera