Agilex 5 - PCIe

[robertzab]

I have a Devkit - MK-A5E065BB32AES1.

I downloaded the examples from the following link:
https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/a5e065b-modular.html

I ran the pcie_ed project and opened Platform Designer to generate the code. During this process, I get the following error:

Error: pcie_ed_pcie_gts_0: set_instance_parameter_value: No parameter sm_hssi_pcie_ctl_x4_ecrc_strip_hwtcl

I didn’t change anything in the project.

I also created a new project and added the “GTS AXI Streaming Intel FPGA IP for PCI Express” IP core, and I’m getting the same error there as well.

How can I fix this, and what does this error refer to?

Quartus - 24.3.1

[Wincent_Altera]

Hi Robert,

I try to download the from the same link as yours and run full compilation in Quartus v24.3.1.

the compilation PASS 100 % without any error.

Another method you may try is to generate from our IP catalog, you may refer the step in 2.2. Generating the Design Example

• I try to compile the same in IP catalog, the result was passing as well, attach the design .qar file as per your reference purpose
• 
• 

Regards,
Wincent_Altera

[robertzab]

Hi,

Thanks a lot for the info and help. It turned out the issue was on Quartus’ or Windows’ side – I solved the problem last night.

Specifically, on a clean Windows installation, I installed Quartus 24.3.1, and synthesis completed successfully without any errors. So I started looking for the issue on my PC.

Since we have different projects, we also use different versions of Quartus, namely 13.0, 18.1, 21, 22, and the latest 24. I checked the Windows PATH, and it pointed to the newest version.

However, I began removing older versions from the system one by one, and only after removing version 21 did the synthesis finally go through correctly in version 24.3.1.

Apparently, some references were assigned to a path they shouldn’t have been.

The main thing is that the problem is solved. Thanks again for your help!