Agilex 5 reconfigurable PLL - emif

[Samo]

Trying to reconfig a PLL with the EMIF Calibration IP 

debug via system console

Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

  enabled dynamic config within IOPLL  and included EMIT Calib.

writing to divide setting addresses -> changes are immediate

multiple pure phase shifts did not work  (work randomly)

is there a bit to start the shift

with one design setting N - M - C worked but no multiple shifts

with an other design problems writing to 0x80 to reset pll after setting NMC, no replay

for new nmc setting  6.4.1 enable | 6.4.2 clear calib | 6.4.3 reconfig | 6.4.4 recal

for just phase shifting 6.4.1 read modify write 6.4.3 without 0x80

2.2.12 perform positive or negative phase shift   -  is there a bit for that? 

Where did I go wrong?

[Farabi]

Hello, 

Section 2.2.12 explains the PLL phase shift feature. 

Phase shift behavior may depend on:

1- PLL locked status

2- Recalibration is triggered or not

3- EMIF IP is actively using the PLL or not

Regarding 0x80 reset is not responding- 0x80 is used to reset the PLL, but you need to make sure the PLL is not in used by EMIF or other IPs, and need to make sure PLL is not in locked status. 

Try to follow below sequence : 

1- Enable Reconfig

2- Clear calibration

3- Write new settings

4- Trigger Recalibration

regards,

Farabi