[Agilex]:Error Sending Bitstream..!!

[raju1421]

Dear Experts,

We are currently working with the Agilex 7 F-Series SOC Development Kit and following the steps outlined in the provided link:
[Agilex PCIe Root Port | Documentation | RocketBoards.org]

However, during the Linux boot-up process, we are encountering the following issues:

“Error sending bitstream!”
“FPGA image is corrupted or invalid.”
“SCRIPT FAILED: continuing…”
" Unable to read file / "

It’s important to note that we are booting from an SD card and using the prebuilt binaries for the PCIe Root Port reference design.

We would greatly appreciate your assistance in resolving the issue and ensuring a successful boot-up process.

Thanks & Regards

 Raju Satrasala 

[Wincent_Altera]

Hello Raju Satrasala,

I understand that you're facing issues with the Agilex 7 F-Series SOC Development Kit during the Linux boot-up process when using the provided prebuilt binaries for the PCIe Root Port reference design.

The error messages you've encountered suggest problems with the FPGA image or other script failures. Let's try to troubleshoot the issue:

FPGA Image Check:

• Verify that the FPGA image you're trying to load is not corrupted. Make sure it was built and programmed correctly. Check the bitstream file and its integrity.

SD Card Check:

• Ensure the SD card is properly inserted, and the files on it are not corrupted. You may want to reformat the SD card and copy the necessary files onto it again.

Boot Sequence:

• Double-check the boot sequence and configuration settings in the board's U-Boot environment. Ensure that the SD card is set as the primary boot device.

File Paths:

• The "Unable to read file /" error suggests that the bootloader can't find the necessary files. Verify that the file paths in your boot script are correctly configured.

Script and Environment Variables:

• Review the boot script and environment variables in U-Boot to make sure they are set up correctly. Ensure that the script points to the right locations for the FPGA image and other essential files.

If you have performed all the suggested tests and ensure that the file that you downloaded from Rocketboard is no problem, please talk with the developer.

I saw there is an open forum page in RocketBoard forum https://forum.rocketboards.org/t/agilex-error-sending-bitstream/3273 file by you as well.

Regards,

Wincent_Intel

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.

[raju1421]

Hi @Wincent_Altera ,

Thank you for your response.

We are utilizing the default wic image from the Intel Agilex® 7 FPGA F-Series SoC binaries archive for SD-Card booting.

However, we are still encountering the error mentioned earlier.

Thanks & Regards

 Raju Satrasala 

[Wincent_Altera]

Hi Raju,

I saw one Intel Article mentioned the same problem as you facing
https://www.intel.com/content/www/us/en/support/programmable/articles/000074735.html

Perhaps you can try the resolution mentioned there and see if this solve your problem or not.

Regards,

Wincent_Intel

[raju1421]

Hi @Wincent_Altera ,

Thank you for your response, but it appears our issue remains unresolved. Please find the attached log for reference.

I have attached a log file for your reference. Please review it and let me know what steps to take next to address our issue.

Thanks & Regards

Satrasala Raju

[Wincent_Altera]

Hi Raju,

Did you add the hps2fpga-bridge node in your device tree.
If not, then please add this. Reference is given on below link-
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt

Please check and ensure you use the correct image file, if not please re-download.

If cannot, I suggest you to file another forum case , please ensure you choose the categories as "embedded" , "HPS" or any related...
The correct support specialist will be there to support you.

Regards,

Wincent_Intel

[raju1421]

Hi @Wincent_Altera ,

Please find the below table for reference 

Switch Configuration
Rocket Board Agilex SOC GSRD	Rocket Board PCI RP	Agilex EVM Working
SW1: ON-ON-ON-ON	SW1: ON-ON-ON-ON	SW1: ON-ON-ON-ON
SW2: All OFF	SW2: All ON	SW2: All OFF
SW3: OFF-OFF-ON-ON-ON-ON	SW3: All OFF	SW3: OFF-OFF-ON-ON-ON-ON-ON-ON
SW4: OFF-OFF-OFF-ON	SW4: ON-OFF-ON-OFF	SW4: OFF-OFF-OFF-OFF

Rocket Board Agilex SOC

https://www.rocketboards.org/foswiki/Documentation/agilexSoCGSRD 

Rocket Board PCI RP

Agilex PCIe Root Port | Documentation | RocketBoards.org

We attempted to utilize the Rocket Board PCI RP Switch Configuration, but encountered issues with detecting the JTAG Chain. However, when we employed the Agilex EVM Working Switch Configuration, we were able to successfully detect the JTAG Chain.

Thanks & Regards

Satrasala Raju

[Wincent_Altera]

Hi Raju,

Glad that you are able to solve this issue and proceed further.
Also, Thanks for sharing with me how you solve this issue. Appreciate that.

Hence, I will set close this forum loop, if you have any further question, feel free to raise another case anytime.

If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me of the cause so that I can learn from it and strive to enhance the quality of future service experiences.

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.

[raju1421]

Hi @Wincent_Altera ,

The issue remains unresolved, despite our modifications to the switch configuration, we have successfully detected the JTAG chain.

Provide me the working files which is present in the 

Agilex PCIe Root Port | Documentation | RocketBoards.org

Thanks & Regards

Satrasala Raju

[Wincent_Altera]

Hi Raju,

Sorry I misunderstand your meaning, and I do not realise you have jtag detection problem at the beginning.
The design at rocketboard shall be correct, could you please re-download and try it again ?
I suspect there might be some corruption when you trying to download it.

Regards,

Wincent_Intel

[raju1421]

Hi @Wincent_Altera ,

Thank you for your response.

I have attempted to resolve the issue by re-downloading the SD Card Image, but unfortunately, I continue to face the same problem.

Is it possible for you to provide the example design files along with detailed building steps for Linux and U-Boot?

Thanks & Regards

Raju Satrasala

[Wincent_Altera]

Hi Raju,

Seen like this issue is more related to Linux booting using U-boot.
For your information, I am support specialist for PCIe IP and design implementation.

Could you please file another forum with title " Linux boot-up failed with Agilex 7 F-Series SOC Development Kit "
for the categories, please ensure you select something related to "embedded" instead of "PCIe".
The correct support specialist should receive your case and continue to support you.

Do you have any queries about PCIe ? If not I would like to have your permission to close this case.

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.

[raju1421]

Hi @Wincent_Altera ,

Thanks for your response.

Please check the below query once and let me know how to solve it.

Compilation Error in Quartus Prime 23.3 for Agilex PCIe Root Port Design Example - Intel Community

Thanks & Regards

Raju Satrasala 

[Wincent_Altera · Accepted solution]

Hi Raju,

Thanks, will close this and move the support to below to avoid any confuse.
Compilation Error in Quartus Prime 23.3 for Agilex PCIe Root Port Design Example - Intel Community

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.