Just found the Altera 1588 solution AN739 as the attached file and downloaded the reference design then try to run it.
When I opened it using Quartus, It shows can't find the qip file as the image.
Error (12006): Node instance "ieee1588_soc_inst" instantiates undefined entity "altera_eth_10g_1588_ref_design_msgdma_top". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 5 warnings
Error: Peak virtual memory: 4892 megabytes
Error: Processing ended: Mon Jul 06 14:07:17 2020
Error: Elapsed time: 00:00:15
Error: Total CPU time (on all processors): 00:00:28
Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 5 warnings
Can anyone help? I just would like to run simulation.
I am trying to implement triple speed ethernet in nios processor using modular scatter gather dma (msgdma) controller. I have build the qsys. For memory i have used ram. I have called 2 msgdma one for receiving in streaming to memory mode and one for transmitting in memory to streaming mode. I have done the interconnections in qsys platform and generated the HDL successfully. The sopcinfo file is also generated. Using this sopcinfo file i tried to generate the bsp. The bsp generates but when i try to build the bsp project in eclipse the build fails. It says that " fatal error. altera_msgdma.h. No such file exists."
I am using Quartus 18.1. I cannot downgrade to lower version as i have progressed a lot in 18.1 and now cannot migrate to a lower version because of dependency issues.
Actually this file is missing in alt_avalon_tse.h. The altera_msgdma.h exists in the installation folder of quartus 18.1 in c drive. But some how when i try to build the bsp it doesn't pick that file and throws the above mentioned error. I have tried to manually move altera_msgdma.h and altera_msgdma.c file into the incude and source file of the driver folder of the project file. After doing this the bsp builds, but the actual project build fails.
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AN739 was developed in year 2016 and meant to be opened with older Quartus v14.0. If you are using later Quartus version then it may bump into error.
Feel free to try out with older Quartus version.
Anyhow, this is just hardware reference design and not for simulation run purpose.
I am trying to implement triple speed ethernet in Cyclone 10 FPGA. I have integrated triple speed ethernet core in platform designer in qsys. If i pump data and do loop back in system side of MAC, its working fine. I am able to monitor Start of packet, data valid, data, End of packet properly in signal tap. Now my aim is that i try to capture the streaming data in system side of MAC directly in Nios side memory. For this i am using Modular Scatter gather DMA. For receive data i am using one MSGDMA in streaming to memory mode and one for transmit data i am using one MSGDMA in memory to streaming mode. I try to capture data in descriptor memory in onchip ram. But i am not getting any data.
I have doubt about my connections of MSGDMA in Qsys.There are no any specific examples detailing how to use MSGDMA with TSE. Some people have done it with SGDMA . I am using quartus 18.1. So how to go about it. How to capture data in onchip RAM.
Alright, so you have get the TSE MAC working and now the issue seems to resides in MSGDMA side, right ?
Unfortunately I am not familiar with MSGDMA but I did found some reference design that you can take a look as reference. It's targeting different FPGA product but the reference design did use TSE and MSGDMA. So, you can check it out
Thank you for the link. I had seen that example. It is implemented in Cyclone V SOC and is using Linux. I am using Cyclone 10 Custom board and want to implement triple speed ethernet using msgdma in Nios.
I am now able to read the pumped input data in Buffer using msgdma. The problem is that how to find out the Packet has started and Packet has ended since i am feeding streamed data. I am struck in this problem.
If possible kindly guide
I presume you are the one that generated the data traffic and verified your own data traffic back in loopback mode,right ? Then you should have your design checking logic to read back and verify your streaming data.
I can tell you from TSE MAC side, we are using start of packet (SOP) and end of packet (EOD) signal to indicate the start and end of data packet flow.
So, you should have implemented your own design checking logic in your NIOS software as well.