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Alternative to altera_mem_if_ddr2_emif?

Altera_Forum
Honored Contributor II
1,137 Views

Hello, 

 

I'm fiddling with a design for the DE2-115, redoing an existing sopc project to fit this hardware. 

 

The existing project have a reference to altera_mem_if_ddr2_emif, which is missing on my installation. I guess this is caused by me having a DE2-115 only :) 

 

Component is named ddr2a. Ports are: 

- global_reset, 

- pll_ref_clk, 

- avl, 

- soft_reset and 

- afi_clk 

 

Module parameters is: 

{CTL_ECC_AUTO_CORRECTION_ENABLED=false, PLL_AFI_HALF_CLK_PHASE_PS_PARAM=0, PLL_CLK_PARAM_VALID=false, MEM_TRP_NS=15.0, PLL_DR_CLK_FREQ_PARAM=0.0, CTL_CSR_CONNECTION=INTERNAL_JTAG, CONTROLLER_LATENCY=5, PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=, CFG_STARVE_LIMIT=10, MEM_TFAW_NS=37.5, CTL_AUTOPCH_EN=false, ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false, CTL_SELF_REFRESH_EN=false, CFG_DATA_REORDERING_TYPE=INTER_BANK, MEM_AUTO_LEVELING_MODE=true, MEM_DLL_EN=true, MEM_BANKADDR_WIDTH=2, MEM_VENDOR=Micron, PLL_ADDR_CMD_CLK_FREQ_PARAM=0.0, MEM_CK_WIDTH=1, PLL_MEM_CLK_MULT_PARAM=0, CTL_CSR_READ_ONLY=1, PLL_AFI_HALF_CLK_DIV_PARAM=0, USE_SEQUENCER_BFM=false, MEM_TREFI_US=7.8, ENABLE_CTRL_AVALON_INTERFACE=true, PLL_DR_CLK_MULT_PARAM=0, TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=-0.01, PLL_P2C_READ_CLK_DIV_PARAM=0, QSYS_SEQUENCER_DEBUG=true, BYTE_ENABLE=false, MULTICAST_EN=false, REF_CLK_FREQ_MAX_PARAM=0.0, DQ_INPUT_REG_USE_CLKN=false, MEM_ASR=Manual, TIMING_TIH=400, ADD_EFFICIENCY_MONITOR=false, TIMING_BOARD_CK_CKN_SLEW_RATE=2.0, PLL_NIOS_CLK_FREQ_PARAM=0.0, NEXTGEN=true, MEM_TWTR=2, MEM_ROW_ADDR_WIDTH=13, RATE=Half, MEM_NUMBER_OF_DIMMS=1, MEM_TRCD_NS=15.0, PLL_DR_CLK_PHASE_PS_PARAM=0, MEM_BL=8, DISABLE_CHILD_MESSAGING=false, MEM_TINIT_US=200, TIMING_BOARD_DQ_EYE_REDUCTION=0.0, MEM_CK_PHASE=0.0, PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=, MEM_CLK_FREQ_MAX=333.333, AUTO_POWERDN_EN=false, PLL_AFI_CLK_MULT_PARAM=0, TIMING_BOARD_SKEW_WITHIN_DQS=0.02, MEM_BT=Sequential, PLL_MEM_CLK_FREQ_SIM_STR_PARAM=, DQS_TRK_ENABLED=false, TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05, SEQ_MODE=0, TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0, FORCE_SYNTHESIS_LANGUAGE=, SOPC_COMPAT_RESET=false, NUM_EXTRA_REPORT_PATH=10, WRBUFFER_ADDR_WIDTH=6, PLL_AFI_CLK_DIV_PARAM=0, PLL_AFI_HALF_CLK_FREQ_PARAM=0.0, PLL_AFI_HALF_CLK_MULT_PARAM=0, PLL_DR_CLK_DIV_PARAM=0, PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=, TIMING_TDSS=0.2, PLL_HR_CLK_DIV_PARAM=0, PLL_WRITE_CLK_FREQ_PARAM=0.0, NIOS_ROM_DATA_WIDTH=32, PLL_CONFIG_CLK_DIV_PARAM=0, PLL_AFI_CLK_PHASE_PS_PARAM=0, MEM_ATCL=0, ADVANCED_CK_PHASES=false, ADDR_ORDER=0, TIMING_TDSH=0.2, CTL_CSR_ENABLED=false, PLL_CONFIG_CLK_MULT_PARAM=0, MEM_TRTP_NS=7.5, TIMING_TDS=300, PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=, COMMAND_PHASE=0.0, AVL_MAX_SIZE=4, PLL_ADDR_CMD_CLK_DIV_PARAM=0, CTL_LOOK_AHEAD_DEPTH=4, SKIP_MEM_INIT=true, CSR_ADDR_WIDTH=16, PLL_MEM_CLK_PHASE_PS_PARAM=0, TIMING_TDH=300, TIMING_BOARD_AC_EYE_REDUCTION_H=0.0, MAX_LATENCY_COUNT_WIDTH=5, MEM_DQ_PER_DQS=8, MEM_DQ_WIDTH=8, TIMING_TDQSS=0.25, TIMING_TDQSQ=240, TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0, CALIB_REG_WIDTH=8, MEM_INIT_FILE=, MEM_INIT_EN=false, TIMING_TDQSH=0.35, TIMING_BOARD_MAX_CK_DELAY=0.6, PLL_CONFIG_CLK_FREQ_PARAM=0.0, TIMING_BOARD_AC_TO_CK_SKEW=0.0, NIOS_ROM_ADDRESS_WIDTH=12, PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=, ENABLE_EXTRA_REPORTING=false, CTL_CMD_QUEUE_DEPTH=8, INCLUDE_BOARD_DELAY_MODEL=false, TIMING_BOARD_SKEW_BETWEEN_DQS=0.02, PLL_MEM_CLK_FREQ_PARAM=0.0, EXTRA_SETTINGS=, AC_PARITY=false, OCT_SHARING_MODE=None, SPEED_GRADE=2, USE_AXI_ADAPTOR=false, CTL_ECC_ENABLED=false, PLL_HR_CLK_MULT_PARAM=0, CFG_REORDER_DATA=true, PLL_WRITE_CLK_MULT_PARAM=0, PLL_CONFIG_CLK_PHASE_PS_PARAM=0, PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0, ENABLE_ISS_PROBES=false, MEM_NUMBER_OF_RANKS_PER_DEVICE=1, PLL_DR_CLK_FREQ_SIM_STR_PARAM=, MEM_DRV_STR=Full, AFI_DEBUG_INFO_WIDTH=32, TIMING_BOARD_MAX_DQS_DELAY=0.6, MEM_NUMBER_OF_RANKS_PER_DIMM=1, RDBUFFER_ADDR_WIDTH=6, DISCRETE_FLY_BY=true, MEM_IF_DQSN_EN=false, READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS, TIMING_BOARD_DQ_SLEW_RATE=1.0, TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.01, PLL_AFI_CLK_FREQ_PARAM=0.0, PLL_HR_CLK_PHASE_PS_PARAM=0, MEM_TMRD_CK=6, PLL_WRITE_CLK_DIV_PARAM=0, DEVICE_DEPTH=1, PLL_NIOS_CLK_MULT_PARAM=0, CTL_DYNAMIC_BANK_ALLOCATION=false, MEM_RTT_NOM=50, ABS_RAM_MEM_INIT_FILENAME=meminit, PLL_P2C_READ_CLK_MULT_PARAM=0, PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0, PHY_CSR_ENABLED=false, PLL_HR_CLK_FREQ_SIM_STR_PARAM=, TIMING_BOARD_DQ_TO_DQS_SKEW=0.0, TIMING_BOARD_TIH=0.0, TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0, PLL_NIOS_CLK_DIV_PARAM=0, CTL_HRB_ENABLED=false, CALIBRATION_MODE=Skip, READ_FIFO_SIZE=8, TIMING_BOARD_AC_SKEW=0.02, CSR_DATA_WIDTH=32, REF_CLK_FREQ_PARAM_VALID=false, TIMING_BOARD_TIS=0.0, MEM_TRRD_NS=7.5, ALTMEMPHY_COMPATIBLE_MODE=false, PLL_WRITE_CLK_PHASE_PS_PARAM=0, SEQUENCER_TYPE=NIOS, CTL_DYNAMIC_BANK_NUM=4, TIMING_BOARD_TDH=0.0, DQS_DQSN_MODE=DIFFERENTIAL, MEM_IF_BOARD_BASE_DELAY=10, PLL_MEM_CLK_DIV_PARAM=0, DAT_DATA_WIDTH=32, MEM_SRT=2x refresh rate, TIMING_BOARD_TDS=0.0, LOCAL_ID_WIDTH=8, MEM_AUTO_PD_CYCLES=0, USE_MM_ADAPTOR=true, MEM_CLK_FREQ=250.0, MEM_TRAS_NS=40.0, PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=false, PLL_C2P_WRITE_CLK_DIV_PARAM=0, MEM_TWR_NS=15.0, REF_CLK_FREQ=50.0, ENABLE_ABS_RAM_MEM_INIT=false, MEM_FORMAT=DISCRETE, MEM_PD=Fast exit, TIMING_TIS=400, MEM_TRFC_NS=105.0, DEVICE_FAMILY_PARAM=, DLL_SHARING_MODE=None, PHY_CSR_CONNECTION=INTERNAL_JTAG, TIMING_TQHS=340, TIMING_BOARD_AC_SLEW_RATE=1.0, DLL_DELAY_CHAIN_LENGTH=10, PLL_C2P_WRITE_CLK_MULT_PARAM=0, MEM_DEVICE=MISSING_MODEL, MEM_TCL=5, ENABLE_BURST_MERGE=false, TIMING_TDQSCK=400, PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=, MEM_MIRROR_ADDRESSING=0, READ_VALID_FIFO_SIZE=16, PLL_ADDR_CMD_CLK_MULT_PARAM=0, PLL_SHARING_MODE=None, PLL_AFI_CLK_FREQ_SIM_STR_PARAM=, PLL_HR_CLK_FREQ_PARAM=0.0, MEM_COL_ADDR_WIDTH=10, PLL_LOCATION=Top_Bottom, PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=, SYS_INFO_DEVICE_FAMILY=Stratix III, DEFAULT_FAST_SIM_MODEL=true, POWER_OF_TWO_BUS=false, PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=, DEBUG_MODE=false, PLL_P2C_READ_CLK_FREQ_PARAM=0.0, MEM_USER_LEVELING_MODE=Leveling, MEM_IF_DM_PINS_EN=true, CTL_USR_REFRESH_EN=false, HCX_COMPAT_MODE=false, PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0, ABSTRACT_REAL_COMPARE_TEST=false, PLL_P2C_READ_CLK_PHASE_PS_PARAM=0, TIMING_BOARD_ISI_METHOD=AUTO, PLL_NIOS_CLK_PHASE_PS_PARAM=0, REF_CLK_FREQ_MIN_PARAM=0.0, TIMING_BOARD_DERATE_METHOD=AUTO} 

 

 

 

Does anyone know this component, and what I might replace it with that is DE2-115 compatible? I'm a bit new to sopc so please forgive me if this is a silly question... 

 

 

Best regards, 

 

M.
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Altera_Forum
Honored Contributor II
138 Views

Hi all.....I ve got an Altera Apex EP20K FPGA with me.To programme it i need to get quartus 1.1 How can i find this version.Is their any method of way of program it using a latest softwares?

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