Amplitude Errors from the ADCs on the CII DSP Board

[Altera_Forum]

I have 2 CII C70 DSP boards with the TI ADS5500 ADCs. I am getting errors in the ADC output for sample frequencies below 50 MHz. To ensure that the errors are just due to the ADC, I ran the following test setup (with the ADC in straight binary mode) and the data acquired by SignalTap: 

 1) A PLL provides the sample frequency to the ADS5500 device 2) The derived data clock from the ADC is used as the sample clock in SignalTap 3) The output pins of the ADS500 are mapped in SignalTap with a 4kB memory 4) ADC output enable is held high and the reset held low 6) A function generator provides a 100 kHz analog input signal 7) A SignalTap list file is used to capture the ADC data and it is plotted in MATLAB.  There are 2 kinds of errors that are identical for both channels on both boards:  1) The loading in the front-end at frequencies up to 15 MHz seems abnormally high. With a 1 MOhm scope probe, 4 Vpp signal is provided from the function generator (2 Vpp into 50 Ohms) through the unconnected cable. When the cable is connected to the SMA, the voltage only reads 1.4 Vpp (at the connector). Because of this attenuation, I can never reach full-scale in the ADC output before I reach distortion. If I put 6 Vpp (3 Vpp into 50 Ohms), then I can see the distortion in the differential signal after the transformers and the ADC output values are maxed out at about 12,000 before I reache distortion.  2) When the sample frequency to the ADC is > 50 MHz, the system responds as expected given the losses in the front end mentioned in 1). However, when the sample frequency is < 50 MHz, there is a "chopping" of the waveform that depends on the input amplitude of the analog signal only. At analog input voltages of less than 700 mVpp, the chopping does not occur. Above 700 mVpp input, the chopping occurs regardless of the analog input frequency. What I mean by chopping is this: When the signal rises from DC and approaches near the peak, the amplitude instantaneously jumps in value by 100-200 points. Then 100-150 points in time later it returns to normal by instantaneously loosing the points it gained. This also occurs on the negative peak.  Additional Test Results:  I carefully measured all three reference voltages (REFP REFM, and IREF) and the common-mode voltage (CM) on the ADC devices and these are solid DC levels of the right value according to the TI data sheet.  Has anyone seen similar behavior?? Suggestions??

[Altera_Forum]

Are you aware that the aoutputs are current outputs and not voltage outputs?

[Altera_Forum]

Here's the data sheet for the ADS55500. http://focus.ti.com/lit/ds/symlink/ads5500.pdf If you go to page 22 you can see the input structure of that converter. Without doing the calculations exactly a mental estimate will give you about a 50 ohm input. That tells you why you have the 2:1 voltage drop from the 50 ohm function generator with/without the A/D load. Almost all of the fast converters have low impedance inputs and that's why on page 24 TI shows you examples of how to drive it.  

 The chopping may be related to the sample and hold input of the ADC needing a stiff driver.  Your 1MOhm probe is NOT 1MOhm at anything but DC. A 15pF probe has 212 ohms of capacitive loading at 50Mhz so that will give you even more voltage drop.  If you want to run an analysis there's an excellent SPICE program that Linear Technology gives away free called LTspice/SwitcherCAD III at http://www.linear.com/designtools/software/. It is actually what Linear uses to design their chips with and is better then about anything you can buy.  My best advice is for you to find a good analog/RF guy for help (yes, I said RF).  Remember, THE WORLD IS ACTUALLY ALL ANALOG, your logic is just fast analog :-)   Al