Apparent size limit for "User hardware1" image on Stratix 10 GX FPGA L-Tile board

[nhadzic]

I am using a Stratix 10 GX FPGA L-Tile board (DK-DEV-1SGX-L-A) and I am burning the binary image to the "User hardware1" section of the on-board flash. So far, the device utilization has been under 25%.

Recently, I added more logic to the design and utilization went up to 56% and now my binary image appears to be "too large". I have a script that generates a 44,032KB .bin file from .pof. The difference between the two utilization is:

- with 25% utilization, the end of the .bin image is all Fs

- with 56% utilization, the end of the image has "real data"

I tried to generate a larger image that goes into the "Zips" space (additional 8,192 KB) but that did not help. It feels like the MAX5 device only looks at the actual "User hardware1" space during configuration.

I also saw there is a "User hardware2" space in the 2nd flash but there is no mention of it in the spec. Maybe that is where the overflow goes?

Note: the actual SOF/POF images are valid and the FPGA works correctly. I just can't configure from flash any more.

Is there a utilization % limitation for the "User hardware1" image?

[NurAiman_M_Intel]

Hi,

Apologize for the delay in response.

You may check below,

Ensure that the flash partitioning is correctly configured. The flash might be partitioned for multiple purposes (e.g., "User hardware1" and "User hardware2"), and it's possible that the image is being placed in the wrong section or that the wrong section is being used to boot. -I think this might be the same as what you suspected

Action: Verify the flash section configuration using Quartus' Flash Programmer tool. Ensure that the "User hardware1" section contains the valid bitstream (SOF/POF image).

Regards,

Aiman

[nhadzic]

Thank you for your response and don't worry about the delays.

Before I continue, I would like to confirm a few items:

• I am using the Quartus Programmer to JTAG configure the FPGA and to burn POF images to the attached NOR flash. Is that what you mean by the "Flash Programmer tool"?
• Is it possible to change the flash configuration in some way? It appears to me that the default configuration size (44,032 KB) is not sufficient to hold binary images for larger FPGA utilization rates.

I just restored my card to the factory fresh setting by using the avst.pof image from the factory_recovery folder. I will repeat my .BIN experiment now and will report the results.

[nhadzic]

I was finally able to perform the experiments: Sorry about the delay.

1. I burned a known good image (FPGA is ~40% utilized). RBF for this image is 38MB. Even though I cannot use RBF,  I like to use it as a proxy for the overall binary image size. This worked.
2. I then generated binary image that contains a larger FPGA image (~52% utilized). This one is definitely larger than the allocated flash space but increased the size of the binary file so it overflows into the next flash range. This experiment did not work. Image is there as my script reads it back and compares the hash against the file we attempted to write.
3. I then repeated step #1 to bring back the card to a working state

So it appears as if MAX-V only looks the "User HW1" location to configure an image from flash. Is there a way to increase the size of the User HW1?

[NurAiman_M_Intel]

Hi,

1. How do you generate .jic file?
2. What do you choose when genrating .jic file?
3. When generating .jic file, you need to define the address.

Regards,

AIman

[NurAiman_M_Intel]

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[nhadzic]

Sorry about the delay.

I don't use .jic file. From what I can gather, .jic file is used for EPCS configuration devices and Stratix 10 GX board uses twp 1Gbit parallel NOR flash devices (PC28FFLxAxSxPH30B85).

- Generate SOF using Quartus Pro

- Convert SOF to POF

- Extract binary from the POF using the example found in the board download package: "examples\board_update_portal\ES\board_update_portal.zip\board_update_portal\build_hw.sh"

File is good, address is good but the resulting binary is larger than the space allocated in HW "User hardware1" space. When that happens, FPGA will not configure successfully from flash. If the image is smaller then everything works fine.

Is using .jic files the official way to burn images on this board? If so, can you please point me to the documentation on how to do it?

Also, what is the purpose of "User hardware 2" space? Is that an overflow for images that do not fit in "User hardware 1" space? There are not details about this space in the board manual or any DIP switches that would let me boot from that space.