I am using a Stratix 10 GX FPGA L-Tile board (DK-DEV-1SGX-L-A) and I am burning the binary image to the "User hardware1" section of the on-board flash. So far, the device utilization has been under 25%.
Recently, I added more logic to the design and utilization went up to 56% and now my binary image appears to be "too large". I have a script that generates a 44,032KB .bin file from .pof. The difference between the two utilization is:
- with 25% utilization, the end of the .bin image is all Fs
- with 56% utilization, the end of the image has "real data"
I tried to generate a larger image that goes into the "Zips" space (additional 8,192 KB) but that did not help. It feels like the MAX5 device only looks at the actual "User hardware1" space during configuration.
I also saw there is a "User hardware2" space in the 2nd flash but there is no mention of it in the spec. Maybe that is where the overflow goes?
Note: the actual SOF/POF images are valid and the FPGA works correctly. I just can't configure from flash any more.
Is there a utilization % limitation for the "User hardware1" image?
