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Honored Contributor I
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Arria V GX Starter Kit

Is Arria V GX Starter Kit (http://www.altera.com/products/devkits/altera/kit-arria-v-starter.html) really available? 

 

I tried to contact Altera sales but they said they don't have this board in their database? The same reply from distributor. 

 

Also, does anybody know about dev board(s) with Arria V GZ?
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Honored Contributor I
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There is a real shortage of this kit, I grabbed one from Arrow a while ago.  

On the website it still says the part number is DK-START-5AGXB3NES, try DK-START-5AGXB3N (product intent part and not engineering sample) and see if they can help you locate one.
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Honored Contributor I
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Thanks! Found it on Altera's web-site - http://www.buyaltera.com/scripts/partsearch.dll?detail&name=544-2742-nd 

 

Do they have reference design for this board with PCIe and chaining DMA example?
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Honored Contributor I
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The example design does not have PCIe yet, although there's a hard macro in the chip. This could also imply you'll need driver support if you plan to drop in PCIe on your own.  

 

In the BTS there is DMA involved in the DDR3 memory test, need to confirm if it already has chaining.
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Honored Contributor I
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Is there a reference design available for this particular board? 

 

Any example of how to set up design for this board, i.e. pin assignments, etc.? 

 

 

--- Quote Start ---  

The example design does not have PCIe yet, although there's a hard macro in the chip. This could also imply you'll need driver support if you plan to drop in PCIe on your own.  

 

In the BTS there is DMA involved in the DDR3 memory test, need to confirm if it already has chaining. 

--- Quote End ---  

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Honored Contributor I
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You can download the install file for reference design and programs from Altera link. Log in may be required. 

ftp://ftp.altera.com/outgoing/devkit/12.1/arriavgx_5agxfb3hf35_start_v12.1.1.1.exe
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Honored Contributor I
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I did not find any PCIe example for this board, however, I modified PCIe ref. design for another Arria V FPGA. 

 

The problem is that PCIe does not come up reliably. I found known issue on Altera's web-site: 

 

http://www.altera.com/support/kdb/solutions/rd03052013_188.html 

 

But even with this workaround PCIe is not reliable. Any ideas on how to make it work properly?
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Honored Contributor I
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Sols, I am in a similar situation .. can you please point us to the "PCIe ref. design for another Arria V FPGA." 

I have the Arria V GX Starter Kei and need ti get something going for X1 / Gen1 asap. 

Thanks, Bob.,
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Honored Contributor I
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Honored Contributor I
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Sols , 

 

I owe you one.... I wonder why I wasn't able to hit this page with all my google searches .. wrong search words I expect. 

I am working second shift tonight as we need to get something going to demo a solution and proof of concept. 

 

Thanks again, Bob.
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Honored Contributor I
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Also, for the chaining dma example there is a Linux device driver ... is there a for the high performance PCIe dma examples above.?

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Honored Contributor I
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Hi all, 

 

I am trying to evaluate the Arria V GX whether it will meet the speed requirements for my design, supposing to run on the Arria V GX Starter Kit. I am using Altera Web edition but this one doesn't seem to support Arria V GX. In the web documentation of the full edition of Quartus I don't see the Arria V GX neither (it has Arria V and Arria V GZ but not GX). The license price is too high just for trying and concluding it might not suit my design. 

 

How did you guys compile your designs? 

 

BR, 

Wim
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Honored Contributor I
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Sols, is there a method documented for converting a design using one Arria chip -> the one on the Starter Kit ? I believe you indicate that is what you did. 

I can chhange the part number but alos need to map the Starter Kit pin allocation as well.
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Honored Contributor I
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I need a Nios II running a some C code and movind data to and from the host ( rc ) memory.  

I sas through the class on the Arria V Hard PCIe IP today and it seems tha tbetween the PCIe  

IP and the NIOS II there is quite some logic to handle PCIe protocol. 

 

I was thinking that logic was in the Hard PCIe IP. I don't need the streaming performance  

more the processing ability of the NOPS II to work through a set of descriptors in the host memory. 

 

IN the DMA examples , I believe the logic I refer to is in the APP level. For the memory mapped  

Avalon PCIe IP, is there a mega function that handles the PCIe traffice at the MM Avalon 

level where data reads and writes to memory are presented as normal bus transactions ? 

 

Thanks, Bob.
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