Arria10 DDR4 Interface

[NikJ]

I am using two DDR4 x16 memories to make it x32 interface. I want to validate my pin selection using a Quartus. When creating example design I do not see x32 memory option. Hence I tried to generate example design by enabling ping-pong memory configuration. However it created two separate CKE/CS/ODT pins for each memory. When I am designing memories for width expansion, it should have single CKE/CS/ODT signals.

Could you let me know what is the right way to create example design for x32 DDR4 interface using two x16 memories.

[BoonT_Intel]

When you attempt to create a width expansion X32 design using 2X16 device. You should not turn on ping-pong phy option. You only need apply all setting same like 2X16 device and change the DQ width to 32.

For ping-pong phy, you only need it when you need 2 independent controllers but you still want to share the same cmd/add pin. However, for CKE/CS/ODT, you still need a different ping for both device because we still need the switching between both devices.

[NikJ]

Thank you for response.

What is the advantage of using ping-pong memory over normal interface with shared CKE/CS//ODT?

I have another query - do I need to supply 0.6V VDDQ/2 to FPGA ?

[BoonT_Intel]

Ping-pong phy solution provide 2 controllers with 2 separate Avalon port. The advantage of ping pong compare to 2 independent controller+interface is it will same some add/cmd pins.

It is hard to say the comparison between​ ping-pong memory over normal (single) interface with shared CKE/CS//ODT. Because the former give 2 user port solutions while second one give only one.

For all voltage that you need supply to FPGA, you can refer to quartus compilation fitter report. Go to pin-out file and you can see every voltage that you need to connect to every FPGA pins.

Hope this helps.