Assign divided clock by internal OSC in constraint

[JW1121]

Hi,

I use MAX10 internal osc to create a clock used as system clock,

however, during compilation there is a warning as follows.

Warning (332060): Node: Clock_Divider:Clock_Divider_inst|clk_div_0[0] was determined to be a clock but was found without an associated clock assignment.

Info (13166): Register CNT[0]~reg0 is being clocked by Clock_Divider:Clock_Divider_inst|clk_div_0[0]

My question is that how to assign this kind of system clock divided by internal oscillator in constraint.

Please refer to the qar file in the attachment.

Regards,

Jamie

[Rahul_S_Intel1]

Hi Jamie, I am requesting to provide the clock source from the dedicated clock pins instead of giving from the clock internal OSC.