Building DDR controller Example Design - Component DDR over Agilex board

[mjuneja2007]

Hello

I am trying to build a DDR controller example design for DDR component memory using Agilex FPGA board - DK-DEV-AGI027-RA.

- I have already created example design as described using "External Memory Interfaces Intel®
  Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide".

- Added pin mapping as per schematic shared over Intel's website.

- Configured power management pin setting and address in Device setting.

- Added timing constraint using sdc file both for PLL ref clock (33.33 MHz) as well as JTAG clock (16MHz) in JTAG sdc template. Timing is also met as verified in timing analyzer.

- Memory clock configured - 1333.33 MHz.

There are no errors or critical warning till SOF file generation. 

But when I try to debug using STP (Signal Tap analyzer file) I am getting cal fail issue. 

Even when I try to debug using System Console (as recommended the user guide), I am getting below error while Creating Memory Interface Connection.

"master_read_32: This transaction did not complete in 60 seconds. System console is giving up."

"An error occurred while running script"::emif_cal_dbg::top::activate_interface_callback":

Can you suggest where I am going wrong and what could be the possible cause of this error.

regards

Madhur

[AdzimZM_Intel]

Hi Madhur,

Which Quartus version that you are currently using?

Have you run the board with example design from the board file?

The design can download from this link: https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agi027.html

Which DDR4 that you are configuring? Is it DDR4 on Bank 2B, 2C or 3C?

Are you already enable the EMIF Debug Toolkit in EMIF IP?

Regards,

Adzim

[mjuneja2007]

Hello Adzim

I compared the example design in the link you shared with my design. I found the pin mapping to be very different.

I was referring to the below schematic.

https://www.intel.com/content/dam/support/us/en/programmable/support-resources/bulk-container/support/boards-kits/agilex/agilex-agi027-devkit-schematic-reva1-apr2021.pdf

While the example design in your link https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agi027.html   refer to different schematic (attached in board design files)

Please confirm which one is correct.

And yes I have enabled "EMIF Debug Toolkit in EMIF IP" in the IP and I am using Quartus version 23.4.3.1.

Note: in the meantime I will generate the SOF file using example design you shared and test it on the board.

Regards

Madhur

[AdzimZM_Intel]

Hi Madhur,

Please help to check for the board version that you have to confirm about the schematic.

You can check in this link by referring to the development kit serial number and the figures.

https://www.intel.com/content/www/us/en/docs/programmable/683288/current/overview.html

Regards,

Adzim

[mjuneja2007]

Hello Adzim

I generated the SOF file using the example design shared over below link https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agi027.html, but that didn't work.

And also I checked the development kit serial number, please find below the requested details.

OPN# DK-DEV-AGI027-RA

Serial number: AGIPCIe8100537

TA#: N2415-001

I even tried to change the DDR parameters as the example design you shared keeping the board setting as DK-DEV-AGI027-RA (where the DDR component lies on bank no. 2B and 2E.) but still same issue occurs (as described in original post).

Please suggest if I need to change any other setting.

regards

Madhur

[mjuneja2007]

Hello Adzim

After some modification in the CAS latency of DRAM controller, I am able to Create Memory connection in the System Console.

But still calibration is failing, with an error code "L1 PASSING WINDOW NOT FOUND".

Here is the memory configuration being read in the System Console.

Can you figure out something out of this info.

Note: I am using this board setting DK-DEV-AGI027-RA (where the DDR component lies on bank no. 2B and 2E.) and pin mapping as per this schematic (https://www.intel.com/content/dam/support/us/en/programmable/support-resources/bulk-container/support/boards-kits/agilex/agilex-agi027-devkit-schematic-reva1-apr2021.pdf)

regards

Madhur

[AdzimZM_Intel · Accepted solution]

Hi Madhur,

Please download the DK-DEV-AGI027-RA/RA-B installer package from the devkit website.

DK-DEV-AGI027-RA/RA-B (v24.3.1 or higher)

The serial number that you have shared is belong to this devkit.

Agilex™ 7 FPGA I-Series Development Kit (Production 2x R-Tile & 1x F-Tile) (Power Solution 2)

DK-DEV-AGI027-RA

AGIB027R29A1E1VB

8100505

Please try to generate the example design based on this devkit and DDR4 setting from this devkit.

Or you can use the existing design in this devkit file.

You also may test the devkit with BTS application but need to use with Quartus version 24.3.1.

From the BTS, you can quick check if there is any error during read and write process of the DDR4 interface.

Regards,

Adzim

[mjuneja2007]

Hello Adzim

After changing the pin mapping as per the schematic shared in DK-DEV-AGI027-RA/RA-B installer package, I am able to resolve the cal fail problem.

I think the above schematic should be updated in the below link as well to avoid confusion.

https://www.intel.com/content/dam/support/us/en/programmable/support-resources/bulk-container/support/boards-kits/agilex/agilex-agi027-devkit-schematic-reva1-apr2021.pdf

Thanks & regards

Madhur Juneja