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Dear Sir / Madam
The custmer needs a clock of 2GHz output of FPGA , I 'm not sure how it achieve? Maybe it can use transceiver lane?
Thanks
Ted
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Hi ,
I am not sure on this HIgh frequency clock generation , PLL will not support this much of high frequency
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Hi ,
Kindly let me know if you need further assistance.
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Hi Rsree
No more questions,Thanks!
Ted
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