Choosing specific PCIe Hard Macro - Arria10GX

[prateekmohan]

Hello,

I am interested in using the Arria10 GX Dev Kit and using the PCIe Hard Macros in them. I have managed to create a PCIe Hard IP in a QSys project but I can't seem to understand how to constrain it to use the specific Hard IP.

From what I understand, there are 4 Hard IPs and the constraint specifies which transceiver lanes (so which banks and which pins) you can use for each of these IPs:

So I thought when I created the IP, in the "Parameters" section I would choose which one of the IPs I am using. However, it doesn't seem to be a parameter to specify this. 

I know I can go into the "Pin Planner" and map out the specific rx and tx lanes and the clk and reset to the correct pins but I wasn't sure if that was the way to do it. How do you know you are selecting the right pins for the PCIe hard macro in that case? Does an error message show up somewhere when you are using the wrong transceiver pins for the specific hard macro?

Thanks!

Prateek

[KhaiChein_Y_Intel · Accepted solution]

Hi Prateek,

The software will issue Fitter error messages if you select the wrong pin. The compilation will stop at Fitter stage.

Thanks

Best regards,

KhaiY

[prateekmohan]

Thanks Khai!

Yup, that worked out. I tried changing some settings in the pin planner and the error appeared in the fitter stage.

Prateek

[KhaiChein_Y_Intel]

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

KhaiY