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FPGA DDR4 Eye Mask

Fresh_Leon
New Contributor I
159 Views

Dear,

 

We are in FPGA (Arria 10) board design progress, our SI engineer are studying on DDR4 simulation.

Where could we find FPGA (Arria 10) DDR4 Eye Mask data (both write and read operation) ?

e.g.

DDR4 write operation eye diagram width & height.

DDR4 read operation eye diagram width & height.

 

Thank you.

 

Brs,

Leon

0 Kudos
1 Reply
Rashmi1
Employee
138 Views

Hello,


Please refer to the A10 EMIF datasheet : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf


The information on eye diagram has been explained in section 11.4.2.2. Understanding Channel Signal Integrity Measurement of the above datasheet.


Thanks.


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