We are in FPGA (Arria 10) board design progress, our SI engineer are studying on DDR4 simulation.
Where could we find FPGA (Arria 10) DDR4 Eye Mask data (both write and read operation) ?
DDR4 write operation eye diagram width & height.
DDR4 read operation eye diagram width & height.
Please refer to the A10 EMIF datasheet : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf
The information on eye diagram has been explained in section 18.104.22.168. Understanding Channel Signal Integrity Measurement of the above datasheet.