Clock Selection Issue with PHYLite IP in DDR Data Capture

[Akshay_A]

I am working on a design where I need to delay calibrating incoming DDR data from an external source and sample the same data to convert it to SDR. To achieve this, I am using the PHYLite IP, which performs both functions.

The clock is provided to the group_0_strobe_in port of the PHYLite IP. However, my design requires two different clocks:

• An internally generated clock for initialization.

• A strobe clock from an external device for real data capture.

To switch between these two clocks, I use the ALTCLKCTRL IP, selecting the appropriate clock based on the operation phase—using the internal clock during initialization and the external gated clock for real data capture. However, the PHYLite IP does not allow an ALTCLKCTRL instance between group_0_strobe_in and the clock inputs.

Is there a way to bypass this restriction and still achieve the required clock switching?

I am using the Altera Arria 10 GX development board with Quartus Prime Pro 24.3 edition.

For better understanding, I have also attached a block diagram illustrating the required input path.

[Zehui]

Hello,

Apologies for the late response.

Unfortunately there is no way to bypass this restriction. group_0_strobe_in must be coming from an external source. The strobe feature of PHY Lite IP is associated with some hardened resources and there is no path for an internal clock to reach these resources.

Thanks.