Connect inclk of PLL to output port of alt_inbuf

[ZhiqiangLiang]

Hi,

I would like to connect crystal oscillator to a general IO pin(e.g. E1) and then use the alt_inbuf to convert the input clock to inclk of PLL.

Please see my verilog code followed.

I am experiencing the error message:

Error (176554): Can't place PLL "nios_core:nios_core_inst|nios_core_PLL_BF:pll_bf|nios_core_PLL_BF_altpll_gka2:sd1|pll7" -- I/O pin clk (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device

the questions are:

1) can I use general IO as crystal oscillator input to PLL?

2) what is wrong with my code bellow?

3) is there any example code about how to use general IO as crystal oscaillator input to PLL?

io_primitives osciin(
.data_in (clk),
.data_out (clk_temp)
);

module io_primitives (data_in, data_out);

input wire data_in;
wire internal_sig;
output wire data_out;

alt_inbuf my_inbuf (.i(data_in), .o(internal_sig));
defparam my_inbuf.io_standard="3.3-V LVCMOS";
defparam my_inbuf.location = "IOBANK_1";
defparam my_inbuf.enable_bus_hold = "on";
defparam my_inbuf.weak_pull_up_resistor = "off";
assign data_out = internal_sig;

endmodule

[FvM]

Hi,

PLL inclk can be only driven by a dedicated clock input pin or the output of another PLL. 

[WZ2]

Hi there,

In general, we do not recommend using GPIO pins as clock inputs. You can refer to the pin-out file to select pins that include the clk_in function.

Best regards.

WZ

[ZhiqiangLiang]

@WZ2 

Thank you!

I know your recommendation.

The problem is that we mistakenly connect crystal oscillator to GPIO pins.

my question is: whether there is a way to make FPGA PLL work when crystal oscillator is connected to GPIO.

[FvM]

Hi,

preventing unlimited routing of PLL clock input is basically intentional action of Quartus fitter, not imposed by lack of connectivity. See discussion in this thread Is there any option to generate 100MHZ clock without PLL in max10 device - Intel Community

I understand that Altera/Intel didn't release "unlimited" PLL inclk routing because it may reduce PLL performance and cause PLL failure under circumstances. Even if it works seamlessly in many cases (I guess so), the remaining problems could cause a big load for Intel support and possibly compromize product reputation.

Regards
Frank

 

[WZ2]

Generally speaking, it’s not feasible, because the structure of a regular GPIO is not sufficient to support PLL operation. This can lead to issues such as the PLL failing to lock or experiencing a delayed lock.

However, from a logic design perspective, you can try the following approach:

You can configure the GPIO pin as an input, connect it to a Clock Bridge IP, and set the output of that IP as a global signal. Then, feed this global signal into the PLL as its input clock.