Couldn't attach the PHY error -19 for Triple Speed Ethernet IP in Quartus Prime

[alvenkatesh]

Dear Team,

We have two FPGA Boards,

1. Intel Cyclone V Based FPGA Custom Board.

2. Zynq Ultrascale+ MPSoC Based FPGA Custom Board.

We want a communication through Ethernet protocol between these two Boards through Backplane connector. We don't have Physical PHY on both boards. We want soft PCS/PMA with MAC everything inside design.

For this, we implemented ethernet design in Zynq Ultrascale+ MPSoC. ( We don't have any problem here).

But for Intel Cyclone V FPGA, we tried to use the

Triple Speed Ethernet IP for Transceiver Options as GXB, that means in 1000Base-X mode and we used MAC with PCS/PMA option inside this TSE IP. And we mapped the differential transceiver lines of this TSE IP to a backplane connector, so that we can connect that board to Zynq Ultrascale+ MPSoC FPGA board in backplane connector and tried to perform Ping test.

But after making design in Quartus Prime for Intel Cyclone V, we tried by booting the board, but eth is not detecting under "ifconfig" in Intel.

We are seeing the following error.

root@socfpga:~# dmesg | grep tse

[    3.240447] altera_tse c0004000.ethernet: Altera TSE MAC version 16.0 at 0xc0004000 irq 104/72

[    3.247835] altera_tse c0004000.ethernet eth1: Could not find the PHY

[    3.247843] altera_tse c0004000.ethernet eth1: Cannot attach to PHY (error: -19)

Also, we tried with fixed-link entry in the device tree instead of phy handle. But still the driver is looking for phy handle and observed the following error.

root@socfpga:~# dmesg | grep tse

[    2.956521] altera_tse c0004000.ethernet: Altera TSE MAC version 16.0 at 0xc0004000 irq 104/72

[    2.964735] altera_tse c0004000.ethernet eth1: No phy-handle nor local mdio specified

[    2.971242] altera_tse c0004000.ethernet eth1: Cannot attach to PHY (error: -19)

For your information, we are trying this TSE with soft PCS PMA (no Physical PHY). We doubt this TSE driver (in kernel 3.10) supports soft phy configuration or not. 

We are attaching the .dts and this error screenshot.

Please kindly review this and guide us to eliminate this Couldn't attach PHY problem in Intel Cyclone V fpga with TSE IP and to detect the eth under ifconfig, which will be supported for ping test on further.

Regards
Venkatesh

[JingyangTeh_Altera]

Hi

I see that in the device tree for the PHY Node, register values is set to 0x0.

You would need to enter a valid i2c value of the PHY IC.

Regards

Jingyang, Teh

[alvenkatesh]

Hi JingyangTeh,

Thanks for the reply. Actually we don't have physical PHY IC, rather we want everything as soft IP inside design itself.

We are not configuring the TSE IP as SGMII mode or RGMII to map to physical PHY (since we don't have).
We are configuring it as transceiver (GXB) 1000 Base-X mode, so that we will be getting differential transceiver line (TXP, TXN, RXP, RXN) which we are mapping backplane connector that will go to another FPGA board.

And the node mention in the device tree is using the physical address which is configured as 0 under PCS options.

I have attached the image below, the pcs option phy id which we are using in the device as a node

So please kindly guide us to solve in this scenario. 

Regards,
Venkatesh

[JingyangTeh_Altera]

Hi

Could you try out the node below for defining the phy for the TSE PCS PHY?

pcsphy0: pcs-phy {

compatible = "altr,tse-pcs-phy";

reg = <0xxxxx 0x4000>; // 0xxx is the TSE Address

};

Regards

Jingyang, Teh