- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello,
I’m working on a design using the Quartus Block/Schematic Editor that requires classic TTL-like logic symbols, e.g., and, or, inverter, f/f. It would be useful if I could build my own primitives with such logic symbols, for example, an “and2” gate with one input inverted.
I looked into doing this with Verilog or VHDL, but as far as I can tell, they only produce rectangular blocks, not logic symbols. I’m now looking at AHDL, which preliminarily seems like it may work.
Questions:
- Am I correct that Verilog/VHDL won’t produce logic symbols for the Block/Schematic Editor?
- If they will, how do I make it happen?
- If they won’t, am I correct that AHDL will?
- If AHDL is the way to go, any suggestions on training and documentation?
- Is there a better way than any of above?
- Anything else I should be aware of?
Many thanks in advance,
Bill McDonald
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
To answer your questions:
- Not exactly, I would say it does and you can see them in the block design file created from the Verilog/VHDL code. But when you insert this symbol in a block design file it will appear as a block.
- I assume you want them to appear as logic symbols in you block design files. I don't think there's a way to do that. You can double-click on them and it will lead you to open the generated bdf file or the Verilog/VHDLfile.
- As far as I know, AHDL will not help. It would be the same as above.
- There is no better way to do what you want to do unfortunately. Just give your symbols and their ports a meaningful name so that it'd be easy for you to remember and visualise.
Regards,
Nurina
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Nurina,
You confirm what I suspected is the case. I'm hoping someone has a solution, so will keep the issue open, but I'm not optimistic.
Thanks for taking time to help!
Bill
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Is the issue just the look of the symbols created from HDL code? I'm pretty sure once you create a .bsf (symbol file) you can edit the look of the symbol to change the rectangle or add to it (little circles for inverters) or move signal labels around. I haven't done it in ages, but I'm pretty sure it's a right-click option there somewhere.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Sstrell,
That's a very good point; it's likely I could use the symbol editor to convert the block into a conventional logic symbol. I've played with the symbol editor some and find it clumsy almost to the point of un-useability, but enduring it once per element to develop a few custom primitives would be worth considerable effort.
Many thanks,
Bill
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
Since your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Regards,
Nurina
P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Nurina,
Sounds good.
Thanks for your help,
Bill

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page