Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Valued Contributor III
2,050 Views

Cyclone III Development board errata

Hello everyone, 

 

I've designed a new system from scratch on the cyclone iii development board (http://www.altera.com/products/devkits/altera/kit-cyc3.html) and I found a few errors in the files provided by Altera. I don't think I've seen them before on the forum, so I thought I would share them with you, so that you don't loose as much time as me to find them out ;) 

 

SRAM pins 

4 pin assignments on the flash/sram data bus are wrong, on the "cycloneIII_3c120_dev_my_first_fpga", "cycloneIII_3c120_dev_niosII_standard" and "cycloneIII_3c120_dev_quartus_pinouts" design examples. 2 of these pins are connected to ground, which makes it somewhat difficult to write what you want in the SRAM. Only the upper word is concerned, so the flash (that only uses the lower word) is not affected. You must change the following assignments: 

fsd PIN_C8 -> PIN_B8 fsd PIN_D9 -> PIN_C8 fsd PIN_F11 -> PIN_D9 fsd PIN_F10 -> PIN_E7 

 

The second error is in the reference manual, page 2-39. It says that the chip select pins for both the character and the graphical LCDs are connected to pin AB24. The chip enable for the text LCD is in fact connected to pin AC24. The example designs are correct though. 

On a personal note I found the name they gave the LCD pins very confusing, because it is impossible to tell which signals are common to the two LCD displays, and which are specific to one of them. I renamed the signals to something like lcd_txt_*, lcd_gr_* and kept only the names lcd_* for common signals. 

 

Is there a way to tell this to Altera so that they can correct all this for the next version?
0 Kudos
16 Replies
Highlighted
Valued Contributor III
7 Views

Hello, 

 

How did you determine the correct pins?
0 Kudos
Highlighted
Valued Contributor III
7 Views

I looked at the schematic. It's the only reliable source of information on Altera's kits.

0 Kudos
Highlighted
Valued Contributor III
7 Views

one more, 

CLKIN_50 is connected to pin AH_15
0 Kudos
Highlighted
Valued Contributor III
7 Views

 

--- Quote Start ---  

one more, 

CLKIN_50 is connected to pin AH_15 

--- Quote End ---  

 

 

And what is incorrect?
0 Kudos
Highlighted
Valued Contributor III
7 Views

Reference manual says, CLKIN_50 is propagated from pin E13. But, these are the actual connections 

pin E13 -> CLKIN_50_EN 

pin AH15 -> CLKIN_50
0 Kudos
Highlighted
Valued Contributor III
7 Views

Could this pin assignment mistake make display creazy? 

In particular a very strange set of characters are visible on my LCD...
0 Kudos
Highlighted
Valued Contributor III
7 Views

Check that you are using the correct FPGA pin for chip select (AC24). 

Are you providing a reset pulse to the LCD before writing to it?
0 Kudos
Highlighted
Valued Contributor III
7 Views

Ciao Daixiwen  

 

yesterday night I solved this issue and I was too tired for reply to my comment. the mistake is linked to misalignment between lcd_out_from_nios and LCD_DATA pinout. They are connected 0 with 7 1 with 6 and so on... 

For the other pin assignment now all it's ok even if I can't find the right associtaion with LCD CONT and I can't change the contrast of my LCD. By take a look to schematic I can't find the pin on DE0 board (NO NANO) that i have to modify in order to change contrast. the only info is LCD_CONT but which is the right pin to use???? 

Anyway really thanks for your support and your help. 

regards
0 Kudos
Highlighted
Valued Contributor III
7 Views

I don't think there is any pin connection to the FPGA to control the contrast. Some LCD modules have a screw you can adjust for the contrast, some others use a special command on the parallel bus, and some use a pin. The the latter group is there is no connection to the FPGA (and it seems to be that way, according to the DE0 manual) then you may need to add a little circuit of your own to control it. 

By the way this thread is about the Altera Cyclone III development board, which is different than the DE0.
0 Kudos
Highlighted
Valued Contributor III
7 Views

The DE0 schematic is pretty clear about the LCD_CONT connection, I think. It's derived from a fixed voltage divider.

0 Kudos
Highlighted
Valued Contributor III
7 Views

Ciao Daixiwen  

 

first of all thanks for fast reply. Sorry if I reported this post in the wrong position, I'll update position.  

Could someone explain to me how this post could be moved from current position to Altera development board..
0 Kudos
Highlighted
Valued Contributor III
7 Views

Ciao FvM  

 

You have reason the schematic is pretty clear but the PINout it's not so clear,  

could you please explain which is the right pin? 

from this post it's not reported: 

http://www.iis.sinica.edu.tw/~johnson/courses/dldl201002/slides201002/de0/de0_v12_release.pdf 

 

from qsf file it's not possible to find 

ftp://ftp.altera.com/up/pub/altera_material/9.1/boards/de0/de0.qsf 

 

 

Could someone please help me? 

 

really thanks
0 Kudos
Highlighted
Valued Contributor III
7 Views

You can see in the schematic that LCD_CONT is only connected to the LCD module and the voltage divider. It has no direct or indirect connection to a FPGA pin. So it won't appear in FPGA pin list or *.qsf file. To make the contrast programmable, you would e.g. connect three resistors in a binary graduation (1:2:4 R) between the voltage divider tap and FPGA outputs. But I don't see the purpose for an evaluation board, may be for a retail product.

0 Kudos
Highlighted
Valued Contributor III
7 Views

good explanation FvM 

I've 2 dark points: 

Usually my lcd is very low contrasted and only by looking with particular angle I can see display contents, but ss soon as I re-boot my board very close to finilize LCD I can see a very good image on display... why? 

 

On my board DE0 I have the follwoing Physical pinout: 

 

GND 

VCC 

CONT 

RS 

RW 

EN 

D0 

.. 

D7 

BL 

GND 

 

my second question is how can I root connection CONT, I have a hole on board but I can't understand how can I write on this pin-out. 

 

Could you please help me, or drive on the right root ? 

 

Thanks
0 Kudos
Highlighted
Valued Contributor III
7 Views

Which LCD module are you using? As far as I know, there's no module shipped with DE0. If you are using a different LCD module than that planned by Terasic, you should check the contrast voltage requirements. It may be necessary to change the voltage divider R11/R14. 

 

As said, the LCD contrast voltage isn't programmable with DE0. In so far, there's no option to change it in software. 

 

You have been talking about low contrast. That's a different thing than switched off back light. I presume that you are able to see the difference.
0 Kudos
Highlighted
Valued Contributor III
7 Views

FvM not I've catched your point no possibilities to control the contrast from FPGA. I have the LCD pin for contrast linked to the board and I can't see a good contrast. Maybe an open circuit could be better!?!?!

0 Kudos