Hi,I have a Cyclone III Starter Board and I already made the myfirstfpga-tutorial (http://www.alteraforum.com/forum/www.altera.com/literature/tt/tt_my_first_fpga.pdf). So I understand the basic functions of this Board and I also wrote some code in VHDL with the Buttons and the LEDs. Now I want to use the DDR-SDRAM, for example write some values into the Memory and read them again. (In this case I don't need communication with PC or other devices). I have found three possibilities to learn how it works:
Your best bet is to take the exact device partnumber and look up the datasheet on the web. Micron for example explains in great detail how their SD-RAMs work, how to operate them and so on and so on. Step 1 is to learn to understand the device.I did the same for the ISSI SRAM on the board (much simpeler than DDR SDRAM but the process is the same) and wrote a controller around it after I understood exactly how the SRAM works.
--- Quote Start --- Your best bet is to take the exact device partnumber and look up the datasheet on the web. Micron for example explains in great detail how their SD-RAMs work, how to operate them and so on and so on. Step 1 is to learn to understand the device. --- Quote End --- The part number of my DDR-SDRAM Chip is psc a2s56d40ctp. I already found the datasheet (http://wiki.laptop.org/images/4/43/a2s56d40ctp-g5.pdf), but it was not very useful for me. --- Quote Start --- I did the same for the ISSI SRAM on the board (much simpeler than DDR SDRAM but the process is the same) and wrote a controller around it after I understood exactly how the SRAM works. --- Quote End --- It seems that writing a controller for DDR-SDRAM from scratch would be a too big project. As I don't have that much time, I decided to use the existing IP-cores from Altera. Yesterday, I spent some time searching in the forum and reading the ddr and ddr2 sdram high-performance controller user guide (http://www.altera.com/literature/ug/ug_ddr_ddr2_sdram_hp.pdf). When I had not really success, I took the qb3_control_panel sample project and modified it a little bit. In the attachment you can see a screenshot of the block diagram file. I don't understand where the input pins for the data, commands, adress, etc. are. It looks like a closed circuit. I thought these blocks are some kind of driver for users like me, that don't want to write a ddr-controller from scratch. But how could I use this...? Which pins should I use? What does this ez_cmdecoder...? Has anyone already worked with ddr_cntr and knows something about these pins and signals like dec_nwr, ddram_data[63..0] or dec_byen[7..0] ?
Hi Stefan,I saw your post about the DDR-SDRAM of Cyclone III Starter Kit. I'm newbie in FPGA, and I need write/read in this memory. In your topic you use the QB3_control_panel example for it. I tried to do this, but I don't have success. Have the license errors when I try to compile the Qb3 example. Error: Can't find valid feature line for core DDR_CNTR (535C_0002) in current license Error (10003): Can't open encrypted VHDL or Verilog HDL file "C:/altera/TentativasMemoria/TesteBaseControlPanel/DDR_CNTR.v" -- current license file does not contain a valid license for encrypted file. How did you do ? Please, help me. Thanks Armstrong
So have you done write and read DDR-SDRAM successfully? can we have more details on how to do that?Thank you very much! --- Quote Start --- Now I have found the solution: Open the qb3_control_panel example project and use signaltap to find out which pin is for what. Then it becomes very easy. --- Quote End ---