Cyclone® IV SDR SDRAM DDR2 Timing Parameter Settings

[Pochi]

I found a document for DDR2 timing parameter settings, but I can't find anything for SDR. I would like to know the setting values of each parameter, so I would appreciate it if someone could help me.

[AdzimZM_Intel]

Hi Pochi,

Which document that you have referred to?

Which IP that you used for SDR? is it SDR or DDR?

Regards,

Adzim

[Pochi]

Dear Adzim

Thank you for your comment.

Sorry for the mixed information.
I will use SDR.

I looked at the document “Interfacing DDR SDRAM with Cyclone Devices” but could not find the individual timing parameters or timing charts for SDR.

Best Regards,

Pochi

[AdzimZM_Intel]

Hi Pochi,

Thanks for your feedback.

I think you might want to look at the sdram controller document in this link: https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/sdram-controller-core.html

Since sdram controller is using avalon transfer, you can refer to avalon interface specification from this link: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/typical-read-and-write-transfers.html

Regards,

Adzim

[Pochi]

Hi Adzim,

Thanks to you, I was able to get most of the information I wanted.
I would like to have the following additional information.

What is the range of the following FPGA settings or characteristics?

1. Output Data High Impedance Time(tHZ)
2. Transition Time of CLK ※Rise and Fall (tR,tF)
3. Data-in Set-up Time(tDH)
4. Data-in Hold Time(tDS)
5. Address hold Time(tAH)
6.CKE Hold Time(tCKH)
7.Exit self refresh to ACTIVE command(tXSR)

Best Regards,

Pochi

[AdzimZM_Intel]

Hi Pochi,

I think the timing setting should be refer to memory datasheet of your memory component.

For example, in page 32 shows electrical characteristics for the memory component in this link: https://www.alldatasheet.com/datasheet-pdf/view/75877/MICRON/MT48LC4M32B2.html

Regards,

Adzim

[Pochi]

Hi Adzim,

Thanks for your feedback.

Sorry for the lack of information.

I would like to know the upper and lower limits of each parameter that can be set in FPGA for memory selection.

Best regards,

Pochi

[AdzimZM_Intel]

Hi Pochi,

I may not understand your question at this point. The setting is to define the memory characteristics.

So, it's limit to what memory has been used.

I don't think the FPGA has that information.

You may clarify your question if I'm not answering your question.

Besides, which IP that you are using and Quartus version?

Regards,

Adzim

[Pochi]

Hi Adzim,

I was able to  the information I wanted.

Thanks.

Best regards,

Pochi

[AdzimZM_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.