FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
4953 Discussions

Cyclone IV set 3.3 volt IO Pins

CLa_R
Novice
489 Views

In my Cyclone IV (EP4CE10) project, I have pin IO set to 2.5Volt.

If I change it from PinPlanner to 3.3volt (3.3-v LVTTL), I obtain an error:

 

Error (169026): Pin ADDR_OUT_A[11] with I/O standard assignment 3.3-V LVTTL is incompatible with I/O bank 4. I/O standard 3.3-V LVTTL, has a VCCIO requirement of 3.3V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 2.5V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard.

 

But The power supply of my FPGA is 3.3V.

How can I change this and obtain a 3.3v for IO pins?

0 Kudos
2 Replies
a_x_h_75
New Contributor III
163 Views

You have some conflicting I/O assignments in your project. You have specified another signal, in the same bank, as having a 2.5V signalling. Check your projects constraints.

 

Regards,

Alex

SreekumarR_G_Intel
163 Views

Thank you a_x_h_75, your suggestion looks correct to me :)

 

Regards,

Sree

Reply