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DDR2/DDR3 SDRAM power decoupling circuitry design

Honored Contributor II


Usually when I place decoupling local capacitors for power supply pins I try to place a capacitor next to each power pin according to manufactor recomended sizing.  

I came to realize that the capacitor sizes and requierd amounts for DDR3 for example are very diffrenet for diffrenet vendors and I couldent find propar guidelines or any equations to help me decide about the capacitors requierd amount and size. 


I found some information in an Altera article from 2005: 

stratix gx board design guidelines (pages 13-24) 


but it is not sufficient to establish a method for placing power decoupling capacitors. 


i would really appriciate your response 

thanks in advance 


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Honored Contributor II

Decoupling became a very difficult matter at the frequencies that we use now. Using one capacitor per pin isn't recommended anymore at high frequencies, especially with BGA chips. It is better to connect the pins directly to the power planes, and put the capacitors around the chip between the power and ground planes. The number and values of the capacitors depend on the frequency/ies the system is running at, power consumption, inductance/resistance of the pins, etc... 

You can search for documents about "power distribution networks" to have more information about the subject. For the Altera side, have a look here (http://www.altera.com/education/training/courses/opdn1100). Most of it should be applicable to the DDR chip too.