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Altera_Forum
Honored Contributor I
1,686 Views

DDR2-SDRAM on Cyclone III DSP Kit (no NIOS)

Hi, 

 

I am using the dsp development kit, cyclone iii edition (http://www.altera.com/products/devkits/altera/kit-cyc3-dsp.html). 

 

I wanted to use the DDR2-SDRAM but unfortunately there is no design example for it. So I used the IP-Core called "DDR2 SDRAM High Performance Controller". There I chose Micron MT47H32M16CC-3 x4 + MT47H32M8BP-3 x1, because that is the same like in the Cyclone III Reference Manual. Then I wanted to connect the FPGA pins to the IP-Core, but I wondered where to connect ddr2top_a[15..0], ddr2bot_a[15..0], ddr2top_ba[2..0], ddr2bot_ba[2..0], etc. 

 

Because on the IP-Core there are only buses called mem_addr[12..0] and mem_ba[1..0]. 

 

I can change Bank Address Width from 2 Bit to 3 Bit and Row Address Width from 13 Bit to 16 Bit, so it matches, but I still have the problem that I have only one output bus(mem_addr) at the IP-Core for the two buses Top and Bottom. 

 

Has anybody the same board and used the DDR2-SDRAM with the FPGA (and without NIOS) ? 

 

Thanks.
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13 Replies
Altera_Forum
Honored Contributor I
151 Views

I haven't used that particular board yet, but look at the example projects distributed with the development board - usually it is straight forward to glean how they use the pins relative to the IP Cores.  

 

Are you intending to use the top and bottom banks of DDR as one wide interface or two independent ones?  

 

Typically you can just duplicate the address lines for the top and bottom (if they have the same depth) but I don't know if you'll meet timing running the signals to both sides of the FPGA, but give it a try.
Altera_Forum
Honored Contributor I
151 Views

 

--- Quote Start ---  

...but look at the example projects distributed with the development board... 

--- Quote End ---  

 

There is none... 

 

 

--- Quote Start ---  

Are you intending to use the top and bottom banks of DDR as one wide interface or two independent ones? 

--- Quote End ---  

 

I don't know. What would be better? 

 

Now the problem is that local_ready (output) is low permanently after the first operation (read or write)... dropping the cl (http://alterauserforums.org/forum/showthread.php?t=3995) didn't help.
Altera_Forum
Honored Contributor I
151 Views

I don't know how to use the inputs local_size and local_burstbegin...

Altera_Forum
Honored Contributor I
151 Views

There is a reference project called cycloneIII_3c120_dev_niosII_standard in the installer. Found here: http://www.altera.com/products/devkits/altera/kit-cyc3-dsp.html 

(http://www.altera.com/products/devkits/altera/kit-cyc3-dsp.html)
Altera_Forum
Honored Contributor I
151 Views

Yes, but I do not work with the NIOS. I use only the FPGA. 

 

My question is specially about the DDR2 SDRAM Controller, how to use local_burstbegin and local_size. It doesn't get clear to me when reading the manual.
Altera_Forum
Honored Contributor I
151 Views

Those signals are described in this document: http://www.altera.com/literature/ug/ug_ddr_sdram.pdf  

From the DDR docs, it seems as though those are avalon signals (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf - look for the section on burst transfers). You can interface to them directly, but why not drop your top level design file into SOPC builder and export the rest of the signals? The SOPC Builder will automagically take care of interfacing to burst enabled slaves even if your master is not.
Altera_Forum
Honored Contributor I
151 Views

 

--- Quote Start ---  

Those signals are described in this document: http://www.altera.com/literature/ug/ug_ddr_sdram.pdf  

From the DDR docs, it seems as though those are avalon signals (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf - look for the section on burst transfers). 

--- Quote End ---  

 

 

I read that but my problem is that local_ready is deasserted after a few write cycles and I do not know why. Reading is no problem but if I write this problem occurs. 

 

I have Quartus 9.0. 

 

PLL Reference Clock = 100 MHz 

Memory Clock = 125 MHz 

Local Interface Clock = 62.5 MHz 

 

 

--- Quote Start ---  

You can interface to them directly, but why not drop your top level design file into SOPC builder and export the rest of the signals? The SOPC Builder will automagically take care of interfacing to burst enabled slaves even if your master is not. 

--- Quote End ---  

 

 

How does that work? I am a beginner in Quartus...
Altera_Forum
Honored Contributor I
151 Views

 

--- Quote Start ---  

...local_ready is deasserted after a few write cycles and I do not know why. Reading is no problem but if I write this problem occurs. 

 

--- Quote End ---  

 

 

Can you post a screen shot of the simulation including all the memory port signals? 

 

 

--- Quote Start ---  

How does that work? 

--- Quote End ---  

 

 

If you mean ... How do you do it, then ... I am assuming you have an HDL design and are attempting to hook up the DDR2 Controller (found in SOPC Builder) - stop me if I'm wrong. You can create a custom component for the HDL entity (top level or not) in SOPC Builder that is attempting to control the DDR. From within SOPC Builder, click File -> New Component. Read the intro, then click the other tabs adding files, specify the top level component, and set which ports compose your component's avalon interface and which should be exported as signals outside of SOPC Builder (ie. to connect to pins or other none SOPC components).  

 

If you mean ... What magic does it perform, then ... this is an interesting read http://www.altera.com/literature/hb/qts/qts_qii54003.pdf. Skip to the section on "Burst Adapters." But basically, the SOPC Builder inserts a state machine to take care of it.
Altera_Forum
Honored Contributor I
151 Views

Hey immutableman, thanks for your help! :) 

 

 

--- Quote Start ---  

Can you post a screen shot of the simulation including all the memory port signals? 

--- Quote End ---  

 

 

Well, I didn't do any simulation. 

 

 

--- Quote Start ---  

If you mean ... How do you do it, then ... I am assuming you have an HDL design... 

--- Quote End ---  

 

 

I have a block design file and there I use some blocks which I created with VHDL. And I just want to read from and write to the DDR2-SDRAM using this Megafunction called "ddr2-sdram high performance controller".
Altera_Forum
Honored Contributor I
151 Views

Glad to be of help. 

 

Okay, how is the DDR core configured? Is it set to Native or Avalon? I'll assume native, in which case the ddr docs say that you have to assert local_wdata_req after the write command has been accepted (see page 3-20 through 21), also set local_size = 1. Can you try this if you haven't and post a signal tap with ALL the signals found in figure 3-13 of the DDR controller docs I linked to above (or at very least all of the local side of the core)?
Altera_Forum
Honored Contributor I
151 Views

Hi stefan! Greetings from Brazil. 

 

I just read your topic where you inquired about how to use the SDRAM controller without Nios... have you been able to do so successfully? 

 

I have the same problem as you did -- I need more memory, but I don't want to use Nios. Actually, it is essential that I do not use Nios, since I am preparing a MIPS processor Verilog HDL design for a Computer Organization and Architecture class. 

 

So far we have been able to do good things with our design -- even simple speech processing and a simple Space Invaders style video game! But for our final projects to reach the next level, we need to provide the students with enough memory to store media. 

 

I would be really thankful if you could give me some pointers! All the material I find online assumes you use Nios. 

 

Thank you for your attention, 

George Brindeiro 

University of Brasília
Altera_Forum
Honored Contributor I
151 Views

Stefan_,  

 

Did you ever have resolution on this?  

 

I am having a similar problem with local_ready from the controller going low and staying low. I know that the controller does get past the calibration stage and starts doing reads and writes. Then at some point, the local ready goes low and the controller stops accepting anything new. If you figured anything out in your design and don't mind sharing, it could be very helpful.
Altera_Forum
Honored Contributor I
151 Views

please check the clocks! This already be discussed here.  

The ddr2_sys clock is not the same like the input clock of DDR2 controller! So if you have 100 MHz clk_in and then use some signals derived from clk_in (like begin_burst, local_write or so), this causes this problem. For all control signals (local_...) you have to use the ddr2_sys clock, which is generatet by ddr2_controller. 

 

Kest
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