DDR4 Reference clock connect from other bank

[smeng12]

您好，客户的S10要接DDR4，开发板的参考设计中DDR的时钟是单独引入的差分时钟，客户想确认如果其他bank接入的时钟然后经过内部PLL再接入DDR的IP是不是也可以，这两种有什么区别，有什么需要注意的吗？谢谢。

[BoonT_Intel]

Hi Sir,

I think what you mean is customer want to connect the reference clock to other bank, and use the internal PLL to supply the reference clock to EMIF IP that located in different bank? For EMIF, this is not allow as this is PLL cascade connection which will generate additional jitter to the clocks. Quartue will give fitter error for this connection.

Also, this connection will not save any PLL resources. This is because for S10, there will have one PLL in each banks. If you place that EMIF in particular banks, it will use the PLL automatically. So, your connection will use additional bank's PLL where you connect the reference clock connect to it.

[BoonT_Intel]

Hi sir, I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.