Hello,I have a DE0-CV working with sdram and onchip memory. When i connect instruction_master with the S1 of the sdram, my system stops working. If I understand the documentation correctly, my system cannot boot from sdram (boot vector + exeception vector cannot be in sdram ) What i an trying to do is to boot from a small onchip memory section and then proceed with a program loaded in the SDRAM. So i installed a small onchip ram section (1024 bytes) and tried to compile my nios sytem. Eclipse reacts with the compile message "region `onchip_memory2' overflowed by 59400 bytes" My question: 1) Is it possible to use the SDRAM for program code? (S1 connecting to instruction_master seems to halt my system.) 2) How do i configure the NIOS system that it locates the majority of the program in the SDRAM after loading the program in fpga ram? remark: l load the system using JTAG, loading the system with the rom on the board is not a target. Thanks for a response John.
There are some tutorials on what you need to do on the Altera web site. Since you don't need to have it power on without loading from JTAG you can save a few steps. First of all, you can delete the on-chip memory since you don't need it to run with JTAG. When creating your system in QSYS, you should unlock all the addresses except the SDRAM which should be locked at address 0. Use the auto assign base addresses command to get the rest of the addresses set up. Change the exception and reset vectors to the SDRAM. Generate the system in QSYS and compile in Quartus. There should be no errors this time. Now you need to go to the software and re-generate the BSP and rebuild both the BSP and your application. This is needed because you've changed the base addresses in QSYS. Now you can load the software. Make sure you have reset the processor and download code checked in the debug/run configuration you use.
Hello Galfonz,Thank you for answering my question. I spent a lot of time (i mean days) with the altera tutorials. I could not get the SDRAM operational on my board. Until the moment i took the demo application from Terrasic and saw that the PLL that drives the SDRAM according to the altera university is not the same as the configuration on the demo cd. So i got the sdram working (data only) based on a redo from scratch based on the terrasic project. I read somewewhere that Terrasic changed the type of SDRAM on the desing at a certain time. So might explain my results. Based on that working design id did what you proposed: - remove on chip ram from the project. - assign base adress 00 to SDRAM - update ram layout - set memory vectors in processor according to new config (select S1. ... ) adress is updated automatically - compile / save / generate QSYS (no errors, some warnings about older type of Nios II processor core) - close qsys and compile verilog in quartus. - download project on DE0-CV (it downloads clearly because my Verlog clock tutorial program i put in the EPROM is no longer showing on the 7seg). - start nios II build tools for eclipse - generate BSP -> error: severe: bsp not valid - delete projects in eclipse and restart wizzard - open SOPC generated by QSYS/Quartus: (checked the compile date and time, so it is the right one) - select hello world application. (project name hello world application) - clean BSP + BUILD All -> Build Finished OK (output shows files were generated) - build Project -> build finished (output shows that files were generated) - right click on project, debug AS select NIOS II and go => It works. Thanks a lot! John.