I have configured the DE0 Nano with a SDRAM, EPCS, and ALTPLL combo that phase shift the SDRAM clock -3ns as required. When I use the flash programmer it completes flashing successfully, restarting the DE0 shows that the VHDL logic is working, but the firmware is not running. Running the system as Nios II Hardware from the nios II ide works fine.I suspected this may be PLL not generating clocks correctly so I instead used the University IP DE clocks , the result is still the same. Assuming that I did not set this system up correctly I ran the the DE0_Nano_QSYS_DEMO downloaded from the terasic website (DE0_Nano_V.1.2.0_CDROM) which contains a project that uses the EPCS,SDRAM, and ALTPLL. The same thing happens, it flashes successfully but the firmware doesn't seem to be loading while the VHDL logic is running fine. I tried this on both Quartus v11.0 and v13. I have also added the nios2-flash-override.txt patch file for EPCS. I've also tried this on two De0 nano boards purchased from terasic (2013) and digikey (2014) thinking the board might be bad but the same result. Everything works fine if I switch from SDRAM to on-chip memory, I can flash and the system runs both hardware and firmware, but I would like to use the SDRAM as the on-chip memory is too small. I'm thinking I need to create a synopsis design constraints file, am I required to create a ".sdc" file when ever I use a PLL? is there somewhere that I can download a recent sample project that has the SDRAM, EPCS and PLL working?
Ok, I understand why nothing was running now. In Qsys for the CPU I had set the SDRAM as the location to start execution but I never copied the application to that starting location. I assumed once I set the SDRAM as the start location the EPCS would automatically know to load into the SDRAM.If I modify the bootloader to load directly into SDRAM then I would not need to use on-chip memory.
You still need some way to get your application code into SDRAM. The easiest way I know of is to use a boot loader in on chip memory.You might also need to have the boot loader set some registers in the SDRAM controller to get it initialized. I'm not sure about that one..
I have now configured the DE0 nano in Qsys with SDRAM and on-chip memory, I'm using Nios II/e CPU with on-chip memory as the reset vector memory, and exception vector memory. So i'm expecting system use the on-chip memory to run firmware and have the sdram available as extra ram. But after flashing it wont load firmware. Is it some how expecting to run from SDRAM?The BSP sets the sdram as the linker target for exception_statck_memory_region_name, and interrupt_stack_memory_region_name automatically, the .heap and .stack liner section points to sdram also. is this causing the problem? This of runs fine with I run as Nios II hardware configuration, just does not boot firmware after flashing.
NVM, got the sdram working, the problem was i needed to set the Qsys component CPU Nios II/e with reset vector and exception vector set as: epcs, and onchip_memory respectively. (I am also using the university IP DE series clocks to do the -3ns phase shift required for SDRAM.To reduce program size I unchecked enable_c_plus_plus and checked enable_small_c_library in BSP editor. this reduced program size by 2KBytes. Everything still works, it flashes and loads firmware fine. There is however a problem that if i edit application and BSP properties and set optimization level to 2 , after i use flash programmer the system does not seem to load firmware. I wonder why, a bug?