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DEO-NANO rolling ADC

Altera_Forum
Honored Contributor II
799 Views

Hello,  

 

I''m pretty new to VHDL and I'm trying to get the DE0-NANO to poll inputs 0-3 and send the data to 4 12 bit registers. I have tried it a numebr of ways but it either didn't work or had some sort of interference. Can anyone help?  

 

Here is my code that was based on the DE0-NANO example.  

 

module ADC_CTRL (  

//  

iCLK, 

iCLK_n, 

oCH0, 

oCH1, 

oCH2, 

oCH3, 

 

oDIN, 

oCS_n, 

oSCLK, 

oCH, 

iDOUT 

); 

 

 

input iCLK; 

input iCLK_n; 

 

 

output [11:0] oCH0; 

output [11:0] oCH1; 

output [11:0] oCH2; 

output [11:0] oCH3; 

output [1:0] oCH; 

 

output oDIN; 

output oCS_n; 

output oSCLK; 

input iDOUT; 

 

reg data =0; // serial address data out  

reg go_en=1; 

wire [1:0] ch_sel= 2'b10; 

reg sclk; 

reg [3:0] cont; 

reg [3:0] m_cont; 

reg [11:0] adc_data; 

reg [11:0] ch0; 

reg [11:0] ch1; 

reg [11:0] ch2; 

reg [11:0] ch3; 

 

 

assign oCS_n = ~go_en; 

assign oSCLK = (go_en)? iCLK:1; 

assign oDIN = data; 

 

assign oCH0 = ch0; 

assign oCH1 = ch1; 

assign oCH2 = ch2; 

assign oCH3 = ch3; 

assign oCH = ch_sel; 

 

// always@(posedge iGO ) 

// begin 

// if(!iRST) 

// go_en <= 0; 

// else 

// begin 

// if(iGO) 

// go_en <= 1; 

// end 

//end 

 

always@(posedge iCLK ) 

//begin 

// if(!go_en) 

// cont <= 0; 

// else 

begin 

if(iCLK) 

cont <= cont + 1'b1; 

end 

//end 

 

always@(posedge iCLK_n) 

begin 

if(iCLK_n) 

m_cont <= cont; 

end 

 

always@(posedge iCLK_n ) 

//begin 

// if(!go_en) 

// data <= 0; 

// else 

begin 

if(iCLK_n) 

begin 

if (cont == 2) 

data <= 0; 

else if (cont == 3) 

data <= ch_sel[1]; 

else if (cont == 4) 

data <= ch_sel[0]; 

else 

data <= 0; 

end 

end 

//end 

 

always@(posedge iCLK) 

begin 

if(!go_en) 

begin // will never get run 

adc_data <= 0; 

ch0 <= 12'h000; 

ch1 <= 12'h000; 

ch2 <= 12'h000; 

ch3 <= 12'h000; 

end 

else 

begin 

if(iCLK) 

begin 

if (m_cont == 4) 

adc_data[11] <= iDOUT; 

else if (m_cont == 5) 

adc_data[10] <= iDOUT; 

else if (m_cont == 6) 

adc_data[9] <= iDOUT; 

else if (m_cont == 7) 

adc_data[8] <= iDOUT; 

else if (m_cont == 8) 

adc_data[7] <= iDOUT; 

else if (m_cont == 9) 

adc_data[6] <= iDOUT; 

else if (m_cont == 10) 

adc_data[5] <= iDOUT; 

else if (m_cont == 11) 

adc_data[4] <= iDOUT; 

else if (m_cont == 12) 

adc_data[3] <= iDOUT; 

else if (m_cont == 13) 

adc_data[2] <= iDOUT; 

else if (m_cont == 14) 

adc_data[1] <= iDOUT; 

else if (m_cont == 15) 

adc_data[0] <= iDOUT; 

else if (m_cont == 1) 

begin 

case (ch_sel) 

2'b00 : ch0 <= adc_data; 

2'b01 : ch1 <= adc_data; 

2'b10 : ch2 <= adc_data; 

2'b11 : ch3 <= adc_data; 

endcase 

// ch_sel = ch_sel + 2'b01; 

end 

end 

end 

end 

 

endmodule
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1 Reply
Altera_Forum
Honored Contributor II
89 Views

Writing testbench to simulate your design to identify which part having the issue.

Reply