Dynamic reconfiguration Native Phy S10 with embedded streamer

[Petkov_Alex]

Hello. I try to simulate NATIVE PHY and ATX PLL for S10. I use 2 profiles switching from GX channel to GXT channel and ATX PLL to as mentioned in document how to use this feature (UG for L-tile S10).
So I created IP cores, Sim files for them and TestBench for it. I wrote Read-modify-write module.
But when I simulate design after my module writes to embedded streamer address 0x540 in several clocks waitrequest goes high, that ok, i know specification for avalon mm bus... Than I begin reading address 0x541, and waitrequest never goes low.

So simulation is strange, I explain. When for example I write to digital or analog reset addresses, everything goes good. But when i write to address embedded streamer or static polarity inversion, reconfiguration avalon waitrequest stuck at high and when I read or write next, it never goes low.

P.S. Quartus Pro 21.4, QuestaSim 10.7c

[Kshitij_Intel]

Hi,

Can you please share your project to debug the issue.

Thank you

Kshitij Goel

[Kshitij_Intel]

Hi,

Please share the project.

Thank you

Kshitij Goel

[Kshitij_Intel]

Hi,

As we do not receive any response from you on the previous reply that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you

Kshitij Goel

[Petkov_Alex · Accepted solution]

Sorry for my late answer, I read document one more time, and understand, that every reconfiguration of S10 Native Phy begin from disable background calibration and end with enable background calibration if it needed. Thanks