I am trying to read a continuous clock signal (125MHz) via IO pin (Bank 8A ,Pin no: L8 ,Pin Name: IO_8A_L8/CLK8P,FPLL_TL_FBP/DIFFIO_RX_T57P)
on my custom made cyclone v fpga board.
FPGA : Cyclone V 5cgxfc9d6
Debugger : USB Blaster Rev C
But when viewed through signal tap what i have observed is as shown below.
The signal is not continuous.
In order to figure out the issue i tapped the incoming signal with DSO , it is continuous. But in signal tap logic analyzer it is not continuous.
Used Internal PLL for generating 300Mhz clock for sampling the signal.
Why this happens.
Kindly help me to resolve the issue.
From the signal tap, I felt like the sampling clock frequency is same or low.
As part of debugging, make one PLL and try to take the out put see pll out put is coming corrctely or not and lock signal is been high.
The above proves that the clock signal is good
Hi @RSree (Intel) ,
What I have mentioned above is there is no lockout situation with the sampling clock & the sampling clock signal is continuous when verified using DSO.
Now also the signal tap analyser is showing the discontinuity.
Is there any issue with the signal tap logic analyser or any other settings i have to do , to tap the high frequency signals.