Errors on Terrasic DE10 board when generating VHDL for HPS using Quartus V20.1 lite

[Sergio_Ma]

I am using Terrasic DE10 board to build a simple HPS with Platform Designer in Quartus V20.1 Lite.

The example that I followed is a youtube video： 

https://www.youtube.com/watch?v=XXMeiVhjaZU

In the video, the author is using Qsys under Quatus V17.x

I have been struggling with HPS for 2 weeks. Never get any HPS succeeding in VHDL generation.

The errors are more or less the same.

Can anyone instruct how I can get rid of these errors to generate fine working VHDL?

I put my hps program into attachment.

Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{D:/intelfpga_lite/20.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Execution of command "{D:/intelfpga_lite/20.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: border: Error during execution of script generate_hps_sdram.tcl: seq: child process exited abnormally
Error: border: Error during execution of script generate_hps_sdram.tcl: seq: add_fileset_file: No such file C:/Users/sergi/AppData/Local/Temp/alt8591_391782329514033884.dir/0004_seq_gen/hps_AC_ROM.hex
Error: border: Error during execution of script generate_hps_sdram.tcl: Generation stopped, 3 or more modules remaining
Error: border: Execution of script generate_hps_sdram.tcl failed
Error: border: 2020.11.26.00:54:22 Info:
Error: border: ********************************************************************************************************************
Error: border:
Error: border: Use qsys-generate for a simpler command-line interface for generating IP.
Error: border:
Error: border: Run ip-generate with switch --remove-qsys-generate-warning to prevent this notice from appearing in subsequent runs.
Error: border:
Error: border: ********************************************************************************************************************
Error: border: 2020.11.26.00:54:29 Warning: Ignored parameter assignment device=5CSXFC6D6F31C6
Error: border: 2020.11.26.00:54:29 Warning: Ignored parameter assignment extended_family_support=true
Error: border: 2020.11.26.00:54:40 Warning: hps_sdram: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors
Error: border: 2020.11.26.00:54:40 Warning: hps_sdram.seq: This module has no ports or interfaces
Error: border: 2020.11.26.00:54:40 Warning: hps_sdram.p0: p0.scc must be exported, or connected to a matching conduit.
Error: border: 2020.11.26.00:54:40 Warning: hps_sdram.as: as.afi_init_cal_req must be exported, or connected to a matching conduit.
Error: border: 2020.11.26.00:54:40 Warning: hps_sdram.as: as.tracking must be exported, or connected to a matching conduit.
Error: border: 2020.11.26.00:54:40 Warning: hps_sdram.c0: c0.status must be exported, or connected to a matching conduit.
Error: border: 2020.11.26.00:54:40 Warning: hps_sdram.p0: p0.avl must be connected to an Avalon-MM master
Error: border: 2020.11.26.00:54:40 Info: hps_sdram: Generating altera_mem_if_hps_emif "hps_sdram" for QUARTUS_SYNTH
Error: border: 2020.11.26.00:54:46 Info: pll: "hps_sdram" instantiated altera_mem_if_hps_pll "pll"
Error: border: 2020.11.26.00:54:46 Info: p0: Generating clock pair generator
Error: border: 2020.11.26.00:54:48 Info: p0: Generating hps_sdram_p0_altdqdqs
Error: border: 2020.11.26.00:55:00 Info: p0:
Error: border: 2020.11.26.00:55:00 Info: p0: *****************************
Error: border: 2020.11.26.00:55:00 Info: p0:
Error: border: 2020.11.26.00:55:00 Info: p0: Remember to run the hps_sdram_p0_pin_assignments.tcl
Error: border: 2020.11.26.00:55:00 Info: p0: script after running Synthesis and before Fitting.
Error: border: 2020.11.26.00:55:00 Info: p0:
Error: border: 2020.11.26.00:55:00 Info: p0: *****************************
Error: border: 2020.11.26.00:55:00 Info: p0:
Error: border: 2020.11.26.00:55:00 Info: p0: "hps_sdram" instantiated altera_mem_if_ddr3_hard_phy_core "p0"
Error: border: 2020.11.26.00:55:00 Error: seq: Error during execution of "{D:/intelfpga_lite/20.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: border: 2020.11.26.00:55:00 Error: seq: Execution of command "{D:/intelfpga_lite/20.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: border: 2020.11.26.00:55:00 Error: seq: child process exited abnormally
Error: border: 2020.11.26.00:55:00 Error: seq: add_fileset_file: No such file C:/Users/sergi/AppData/Local/Temp/alt8591_391782329514033884.dir/0004_seq_gen/hps_AC_ROM.hex
Error: border: while executing
Error: border: "add_fileset_file $file_name [::alt_mem_if::util::hwtcl_utils::get_file_type $file_name 0] PATH $file_pathname"
Error: border: ("foreach" body line 4)
Error: border: invoked from within
Error: border: "foreach file_pathname $return_files_sw {
Error: border: _dprint 1 "Preparing to add $file_pathname"
Error: border: set file_name [file tail $file_pathname]
Error: border: add_fileset_file $..."
Error: border: (procedure "generate_sw" line 18)
Error: border: invoked from within
Error: border: "generate_sw $name $fileset"
Error: border: ("if" then script line 4)
Error: border: invoked from within
Error: border: "if {[string compare -nocase $fileset QUARTUS_SYNTH] == 0} {
Error: border: set top_level_file "altera_mem_if_hhp_qseq_synth_top.v"
Error: border: add_fileset_file $top_level_fi..."
Error: border: (procedure "generate_files" line 4)
Error: border: invoked from within
Error: border: "generate_files $name QUARTUS_SYNTH"
Error: border: (procedure "generate_synth" line 3)
Error: border: invoked from within
Error: border: "generate_synth altera_mem_if_hhp_qseq_synth_top"
Error: border: 2020.11.26.00:55:00 Info: seq: "hps_sdram" instantiated altera_mem_if_hhp_ddr3_qseq "seq"
Error: border: 2020.11.26.00:55:00 Error: Generation stopped, 3 or more modules remaining
Error: border: 2020.11.26.00:55:00 Info: hps_sdram: Done "hps_sdram" with 7 modules, 33 files
Info: border: "hps_io" instantiated altera_interface_generator "border"
Error: Generation stopped, 1 or more modules remaining
Info: hps: Done "hps" with 21 modules, 68 files
Error: qsys-generate failed with exit code 1: 66 Errors, 4 Warnings
Info: Finished: Create HDL design files for synthesis

[Sergio_Ma]

The board is DE10 standard board.  Cyclone V 5CSXFC6D6F31C6

[EBERLAZARE_I_Intel]

Hi,

I recommend you refer below design instead:

https://rocketboards.org/foswiki/Documentation/CycloneVSoCGSRD