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Failure Analysis request for field-failed Altera's FPGAs

JP1
Beginner
900 Views

Hello Altera Team.

 

Unfortunately our customer Cisco reported field failures on 1 of their units. After performing a FA on this unit, we found that it is related to one Altera's FPGA...

Please find attached the info obtained by our FA Team in regards to this case.

Could you please help with a FA from your side to validate the RC on this issue?

 

Thanks in advance!

 

@Zawani_M_Intel 

0 Kudos
9 Replies
Zawani_M_Intel
Employee
862 Views

Hi JP1,

 

From the attachment, I understand that 'PWR_P1V2 50 ohms' 'Golden PWR_P1V2 108 ohms' . Can you confirm the pin name so I can comment further on your issue?

 

Thanks!

 

Wani

Zawani_M_Intel
Employee
845 Views

Hi JP1,

 

Is there any update to previous conversation?

 

Wani

Zawani_M_Intel
Employee
819 Views

Hi JP1,

 

Can we have any update to this request?

 

Wani

JP1
Beginner
797 Views

Hello Wani.

Sorry for my late reply. I confirmed with the FA Team that the affected pin name is PWR_P1V2, it has a lower impedance than it should be.

 

Regards!

JP1
Beginner
760 Views

Hello Wani.

Did you have chance to review the info provided? Please let me know if there is something else needed from our side to move on with this FA request.

 

Regards!

Zawani_M_Intel
Employee
747 Views

Hi JP1,

 

PWR_p1v2 is refer to power pins.

 

From on the attachment ;

4-We perform measurements on the FPGA
RESULT=Fail
RMA_PWR_P1V2 ---->50 ohms

Golden
PWR_P1V2 ---->108 ohms

 

5-We carry out an inspection with the help of the thermal camera
Result = Fail
The MIFPGA shows a point with very high temperature

 

Based on the statement, we can see the failure symptoms is because of electrical Overstress (EOS).

EOS occurs when excess voltage or current flows in a circuit, which can cause further damage and causing major damage.
In this case, we can see the EOS caused the failure when the reading of the good and bad units is in huge difference. When the resistance is low, means that the current/voltage is high. The FPGA get unwanted current/voltage beyond its operating specs.

In order to avoid electrical damage, the device should always be handled in a static-free environment and all the input signals should remain within specified limits, as recommended in the PSG Data Book and associated application notes, at all times.

 

I hope this will help to clarify.

 

Wani

JP1
Beginner
740 Views

Hello Wani.

Thanks for the feedback. Let me check with our FA engineers to know their opinion.

 

Regards!

JP1
Beginner
468 Views

Hello Wani.

 

Sorry for my lack of follow up upon this case.

I checked with Cisco folks and despite this could be a clear EOS damage, they are very interested in having an analysis from your side due this is an End Customer Requested case.

Is there any chance for you to help us with the case? We'll need to deliver the FAR to Cisco so the case can be consider as closed, so your support will be much appreciated.

 

Regards!

Zawani_M_Intel
Employee
420 Views

Hello JP1,

 

No worries, I'm happy to help you on this issue.

We can discuss further regarding this topic in private email as some confidential info is required.

 

Thanks!

 

Regards,

Zawani

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