Hello Altera Team.
Unfortunately our customer Cisco reported field failures on 1 of their units. After performing a FA on this unit, we found that it is related to one Altera's FPGA...
Please find attached the info obtained by our FA Team in regards to this case.
Could you please help with a FA from your side to validate the RC on this issue?
Thanks in advance!
From the attachment, I understand that 'PWR_P1V2 50 ohms' 'Golden PWR_P1V2 108 ohms' . Can you confirm the pin name so I can comment further on your issue?
PWR_p1v2 is refer to power pins.
From on the attachment ;
4-We perform measurements on the FPGA
RMA_PWR_P1V2 ---->50 ohms
PWR_P1V2 ---->108 ohms
5-We carry out an inspection with the help of the thermal camera
Result = Fail
The MIFPGA shows a point with very high temperature
Based on the statement, we can see the failure symptoms is because of electrical Overstress (EOS).
EOS occurs when excess voltage or current flows in a circuit, which can cause further damage and causing major damage.
In this case, we can see the EOS caused the failure when the reading of the good and bad units is in huge difference. When the resistance is low, means that the current/voltage is high. The FPGA get unwanted current/voltage beyond its operating specs.
In order to avoid electrical damage, the device should always be handled in a static-free environment and all the input signals should remain within specified limits, as recommended in the PSG Data Book and associated application notes, at all times.
I hope this will help to clarify.
Sorry for my lack of follow up upon this case.
I checked with Cisco folks and despite this could be a clear EOS damage, they are very interested in having an analysis from your side due this is an End Customer Requested case.
Is there any chance for you to help us with the case? We'll need to deliver the FAR to Cisco so the case can be consider as closed, so your support will be much appreciated.