Thanks for your answer. I still have 2 questions.
1. By vhdl programming, is "signal cnt_comm_cycle : integer range 0 to 6 := 0;" meaning that I have defined the initial value? If that, can I set the initial value to 1 ( "signal cnt_comm_cycle : integer range 0 to 6 := 1;" )? Because I find that sometimes when I set an initial value not equaling 0, then the total code is wrong (RTL simulation is fine, but downloading to the board is not working correctly). Then I just change the defined initial value to 0, and use a reset to reset the signal to 1, and it seems to work. Is there some settings in Quartus to make sure that setting initial value is valid?
2. And for the state machine initial value, for the following two lines,
type t_SM is (IDLE, PRE_STRB, PRE_START, START, IN_FRAME, PRE_STOP, STOP);
signal state : t_SM := IDLE;
Is it meaning that the initial state will be IDLE after the board is powered up?
There is no setting in Quartus to ensure these initial values are observed. The power up value of the registers is determined by the FPGA technology/family.
If you want to guarantee a particular value in a register prior to your logic running you will have to use a reset signal.