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Hi i am implementing a HDMI module, everything went well when i am assigning the pins and simulating it i am getting an error and i am unable to get around.

MFort6
Beginner
151 Views

kit : Arria V GX 5AGXFB3H4F35C4N

Code:

////////////////////////////////////////////////////////////////////////

module HDMI_test(

input pixclk,

output [2:0] TMDSp,

output TMDSp_clock

);

////////////////////////////////////////////////////////////////////////

reg [9:0] CounterX = 0;

reg [9:0] CounterY = 0;

reg hSync, vSync, DrawArea;

reg rst = 0;

always @(posedge pixclk) DrawArea <= (CounterX<640) && (CounterY<480);

 

always @(posedge pixclk) CounterX <= (CounterX==799) ? 0 : CounterX+1;

always @(posedge pixclk) if(CounterX==799) CounterY <= (CounterY==524) ? 0 : CounterY+1;

 

always @(posedge pixclk) hSync <= (CounterX>=656) && (CounterX<752);

always @(posedge pixclk) vSync <= (CounterY>=490) && (CounterY<492);

 

////////////////

wire [7:0] W = {8{CounterX[7:0]==CounterY[7:0]}};

wire [7:0] A = {8{CounterX[7:5]==3'h2 && CounterY[7:5]==3'h2}};

reg [7:0] red, green, blue;

always @(posedge pixclk) red <= ({CounterX[5:0] & {6{CounterY[4:3]==~CounterX[4:3]}}, 2'b00} | W) & ~A;

always @(posedge pixclk) green <= (CounterX[7:0] & {8{CounterY[6]}} | W) & ~A;

always @(posedge pixclk) blue <= CounterY[7:0] | W | A;

 

////////////////////////////////////////////////////////////////////////

wire [9:0] TMDS_red, TMDS_green, TMDS_blue;

TMDS_encoder encode_R(.clk(pixclk), .VD(red ), .CD(2'b00)    , .VDE(DrawArea), .TMDS(TMDS_red));

TMDS_encoder encode_G(.clk(pixclk), .VD(green), .CD(2'b00)    , .VDE(DrawArea), .TMDS(TMDS_green));

TMDS_encoder encode_B(.clk(pixclk), .VD(blue ), .CD({vSync,hSync}), .VDE(DrawArea), .TMDS(TMDS_blue));

////////////////////////////////////////////////////////////////////////

wire clk_TMDS, DCM_TMDS_CLKFX; // clk x 10 = 250MHz

TMDS_clk uut (

.refclk(pixclk),  // refclk.clk

.rst(rst),   //  reset.reset

.outclk_0(clk_TMDS) // outclk0.clk

);

reg [3:0] TMDS_mod10=0; // modulus 10 counter

reg [9:0] TMDS_shift_red=0, TMDS_shift_green=0, TMDS_shift_blue=0;

reg TMDS_shift_load=0;

always @(posedge clk_TMDS) TMDS_shift_load <= (TMDS_mod10==4'd9);

 

always @(posedge clk_TMDS)

begin

TMDS_shift_red  <= TMDS_shift_load ? TMDS_red  : TMDS_shift_red [9:1];

TMDS_shift_green <= TMDS_shift_load ? TMDS_green : TMDS_shift_green[9:1];

TMDS_shift_blue <= TMDS_shift_load ? TMDS_blue : TMDS_shift_blue [9:1];

TMDS_mod10 <= (TMDS_mod10==4'd9) ? 4'd0 : TMDS_mod10+4'd1;

end

 

OBUFDS OBUFDS_red (.I(TMDS_shift_red [0]), .O(TMDSp[2]));

OBUFDS OBUFDS_green(.I(TMDS_shift_green[0]), .O(TMDSp[1]));

OBUFDS OBUFDS_blue (.I(TMDS_shift_blue [0]), .O(TMDSp[0]));

OBUFDS OBUFDS_clock(.I(pixclk), .O(TMDSp_clock));

endmodule

 

 

0 Kudos
2 Replies
Deshi_Intel
Moderator
128 Views

Hi,

 

Alright, I can see that you faced Quartus fitter compilation error.

 

From the pin planner assignment, I can see that you mix up 2.5V and 1.5V IO standard for the same HDMI pins.

  • Ideally, all HDMI pins should be set to 1.5V PCML and not to be mixed with 2.5V IO standard, right ?

 

One quick suggestion is you can remove you pin assignment setting and let Quartus auto fit the pin assignment for you as reference . Then only you modify from there.

 

But if you need my help to really nail down the fitter error issue then I need your help to archive your Quartus design into *.qar file and share with me to review which path goes wrong in your design.

 

Thanks.

 

Regards,

dlim

Deshi_Intel
Moderator
128 Views

HI,

 

I have not hear back from you after my last feedback on May 29.

 

Hopefully you already resolved the fitter issue and able to proceed with you project development

 

For now, I am setting this case to closure first.

 

Feel free to file new forum thread if you still have enquiry in future.

 

Thanks.

 

Regards,

dlim

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