High Speed Intel Reed Solomon Simulation Model Submodules are being generated in VHDL although i select Verilog Simulation Model

[CheePin_C_Intel]

Hi Oren, As I understand it, you are observing the submodules simulation models are generated in VHDL even though you have selected Verilog. For your information, I have managed to replicate similar observation by using Q17.0. It seems like only top level files are affected by the Verilog or VHDL selection. Based on this observation, I believe there is only one version of submodules models, which is in VHDL available currently. Sorry for the inconvenience. Please let me know if there is any concern. Thank you. Best regards, Chee Pin

[OLevy1]

Hi Chee,

thank you for the quick answer.

this is a real problem for me since i am using simulation tool that supports ONLY Verilog.

purchasing this Core i took into account i would be able to use it (and by saying 'using' i mean 'simulate' and 'compile' with the tools i already have).

right now, according to your answer, since there is a mistake and this core documentation is misleading, i need to upgrade the tool i am using for simulation.

i would like to have a solution for this one.

thanks,

Oren

[CheePin_C_Intel]

Hi Oren, May I know which simulation tool that you are currently using? Just wonder if you have had a chance to try with Modelsim* Intel® FPGA Starter Edition to see if it works for you? Thank you.

[OLevy1]

Hi,

i am using ModelSim DE 10.3d

Oren

[CheePin_C_Intel]

can you try using the Modelsim* Intel® FPGA Starter Edition which come with Quartus installation and free.

[OLevy1]

what is the difference between 'Modelsim* Intel® FPGA Starter Edition' and the 'ModelSim DE 10.3d' i am using? if its free and has the same features i might consider working only with the 'Modelsim* Intel® FPGA Starter Edition'.

i will try and update

[OLevy1]

hi,

my entire simulation env. is already written so i tried to compile it with the Starter Edition.

i have managed to compile most of it except for the following command which i get an error message:

vlog -sv12compat -timescale 1ns/1ps -l logs/build.log -suppress 2227,2240,2897,2083,139 ../../FPGA/4x10/MAC/Branches/v5042_oren_dbg/tb/top_tb.sv "+incdir+../../FPGA/4x10/MAC/Branches/v5042_oren_dbg/src/stx5" "+define+BFM_LANES=4" "+define+BFM_PIPE=1" "+define+BFM=top_tb.gpipe.bfm" "+define+CHUNK_SIZE=38880" "+define+NUM_OF_CYCLES_AFTER_RESET_BEFORE_START_OF_INJECTION=12" "+define+DATA_BIN_PATH="../../FPGA/4x10/MAC/Branches/v5042_oren_dbg/tb/"" "+define+TEST_NAME=base_fec_adj2" -work work/sim -L xgpon_design -L pcie_hip_com -L reconfig_desi_com

# extra characters after close-quote

do you know why?

thanks,

Oren

[OLevy1]

hi,

i have tried running the simulation env. using the Starter Edition and i am having many errors (which i dont have when i use the ModelSim DE 10.3d).

i will need your help with this one.

thanks;

Oren

[CheePin_C_Intel]

Hi Oren, Sorry for the delay. By looking at your previously attached error, sorry as I could not really tell what might be wrong with the compilation. It seems like some type with "extra characters after close-quote" message. As a workaround, I would like to suggest you to start by configuring the IP to your target configuration, then use Generate -> Generate Example Design to generate the example design from the IP. Then try to compile the design using the msim_setup.tcl in Modelsim. Once you are able to compile and get the simulation running. Then you may try to customize from there to your target requirement. Please let me know if there is any concern. Thank you. Best regards, Chee Pin

[CheePin_C_Intel]

Hi Oren, Just would like to follow up with you on this. Thank you.