The hard processor system (HPS) clock generation is centralized in the clock manager. The clock manager is responsible for providing software-programmable clock control to configure all clocks generated in the HPS. Clocks are organized in clock groups. A clock group is a set of clock signals that originate from the same clock source. A phase-locked loop (PLL) clock group is a clock group where the clock source is a common PLL voltage-controlled oscillator (VCO).
Some development kits are supporting the Clock Select (CSEL) switches, which are used to define the source of input clock to HPS PLL. ARM processor can run on up to 1GHz MAX.
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