I am doing a project with altera Cyclone 4 GX development board, I have few queries,
- initially the PCIE Card on Development board was not detected even for example designs of Quartus 18.1 version, (i doubt the free_100MHz clock pin which i give to pll clock), Please suggest me what could be the issue.
- Example design of 10.1 Quartus version is working, now i want to generate some memory TLP to check the application layer that i have generated, i have used pcie tree, but in signal tap i couldn't see any waveforms, once i stop running i see some message tlp data in rxdata, rxbardec=01, rx_be=0f.
Note: i used app_clk from pcie_core as trigger.
please help me how can i generate memory tlp packets to debug my code and validate in signaltap.
I have read the pcitree user guide, but couldn't finf what kind of tlps are being generated. Also when i checked in Logic Analyser i was receiving only message TLP with auto read/write.
Please send me if any detailed guidelines are present for sending 3DW memory TLPs from PCITree.