I am doing a project with altera Cyclone 4 GX development board, I have few queries,
Note: i used app_clk from pcie_core as trigger.
please help me how can i generate memory tlp packets to debug my code and validate in signaltap.
I have read the pcitree user guide, but couldn't finf what kind of tlps are being generated. Also when i checked in Logic Analyser i was receiving only message TLP with auto read/write.
Please send me if any detailed guidelines are present for sending 3DW memory TLPs from PCITree.