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URN
Novice
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Accessing RAM from custom IP in Platform Designer.

Does anyone have a simple example of Verilog to access RAM within an SOPC block as a custom IP with Avalon MM interface? Thanks.

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GuaBin_N_Intel
Employee
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We have some tutorial and video on how to build a new avalon-mm IP, either find in google "Making Qsys Components Tutorial" or https://www.youtube.com/watch?v=v6rhbVABlo8. To access it, you have a master interface that compatible to avalon-mm spec https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf, Figure 7.

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