How to implement Rs OCT on Cyclone V LVDS differential output IOs ?

[FPINE1]

Hello, with Cyclone V Rs and Rd OCT possibilities it seems that differential links between FPGA and SFP transceiver (for instance) does not need external series and differential terminations (according to some demo boards schemas). Via Quartus pin planner I have instantiated input LVDS IOs with Rd OCT, but did not managed to instantiate Rs OCT on LVDS output IOs:

-   Are Rs OCT instantiated by default when configuring an output IO as LVDS output IO?

-   If not, to instantiate Rs OCT on a differential link does I have to configure the output differential IO into an other “I/O standard” than LVDS => “differential 1.8-v SSTL class II” for example?

Thank for your help 

[Rahul_S_Intel1]

Hi ,

May I know exactly which IO standard your referring , In the below document, the supported oct is given for all the IO standards . Refer page no: 143

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf