How to transfer data from FPGA to HPS DDR

[2258432]

Hi,

I have two cyclone V soc boards, and I am working on a design to transmit video data generated from the FPGA side of the first board to the second board through HPS Ethernet, and finally display it through HDMI.

In https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/How-to-correctly-read-data-from-FIFO-on-HPS-and-send-it-out/m-p/1501530/emcs_t/S2h8ZW1haWx8dG9waWNfc3Vic2NyaXB0aW9ufExKTkxLVEc3VVRJVUg1fDE1MDE1MzB8U1VCU0NSSVBUSU9OU3xoSw#M25152 , I used a 32 bit wide and 2048 deep FIFO on the sending and receiving boards to store data. But now I feel that this method is not reliable. I want to use HPS DDR to store my video data, read the data from HPS DDR on the HPS side, and send it.

I don't understand how HPS DDR works. I found a method to write data to HPS DDR: https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/writing_to_hps_memory , and I tried it according to its method and succeeded.

However, I still don't know the method to transfer data from FPGA to HPS DDR. I know that I should use mSGDMA, but I'm not sure about the specific work.

Another question is whether the receiving board should use the DMA PL330 internal to HPS to send data from HPS to HPS DDR instead of mSGDMA？

Can someone tell me the general steps or provide some examples for writing data into HPS DDR?

Thank you in advance.

[AdzimZM_Intel]

Hello,

I'm Adzim will assist you in this thread.

Based on my understanding, you want to use DDR interface that connect to HPS and want to know how to send the data from FPGA side to DDR interface in HPS side.

In that case, the HPS IP has a port "f2h_sdram" that can transfer the data into the SDRAM.

You need to connect the port with the Avalon Memory Mapped Master or AXI such as mSGDMA module.

Sorry, we don't have an example design for HPS DDR.

But I think you can check on other example design such mSGDMA example design for a showcase the use of mSGDMA. https://community.intel.com/t5/FPGA-Wiki/MSGDMA-design-example/ta-p/735335

Anyway, you can find all reference design available in FPGA Design Store in Intel website. https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-store.html

Regards,

Adzim

[2258432]

Hello Adzim,

Thanks for your help. I have referred to writing_to_hps_memory  and made modifications to my design. As you said, I used F2H_ SDRAM bus, but my confusion is how to control mSGDMA to transfer data into HPS DDR through the F2H_SDRAM bus. In writing_to_hps_memory ,control mSGDMA by writing a program on the HPS side. However, I need to write a program on the HPS side to send data from HPS DDR. Therefore, I want to add a nios II in qsys (platform designer) to control mSGDMA for data transmission. I don't know if this is feasible.

If possible, could you tell me some details about mSGDMA, such as how I should operate it for data transfer.

Best regard.

platform designer

[AdzimZM_Intel]

Hello,

I'm not so used to mSGDMA module. There are some resources for the mSGDMA module in the Embedded Peripherals IP User Guide. Link: https://www.intel.com/content/www/us/en/docs/programmable/683130/23-1/modular-scatter-gather-dma-core.html

mSGDMA Design Example: https://community.intel.com/t5/FPGA-Wiki/MSGDMA-design-example/ta-p/735335

I'm sorry if I can't help you for this question. But you still can create another thread and ask for that specific question.

Regards,

Adzim

[2258432]

Hi,

Thanks again for your help. I would like to ask another question, how to read data from HPS DDR on the HPS side? Can I use the mmap function to do this? If possible, I don't know the mapping address for HPS DDR. In https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html , I didn't find the address for HPS DDR.

regards.

[2258432 · Accepted solution]

After  testing, using the mmap function on the HPS side can read data from HPS DDR. I referred to https://github.com/zangman/de10-nano/blob/master/docs/FPGA-SDRAM-Communication_-Avalon-MM-Host-Master-Component-Part-3.md  and used the mmap function to operate on HPS DDR, resulting in the same results as Zangman's.

In cycloneV soc(de10-nano), the starting address of HPS DDR is 0x0000000 and the ending address is 0x3FFFFFFF.

/* code for operating HPS DDR */
#include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include <sys/mman.h>

#define HPS_DDR_BASE 0x00000000
#define HPS_DDR_SPAN 0x40000000
#define HPS_AXI_BASE 0xC0000000

int main() {
    int fd;
    void *hps_ddr_base;
    void *h2f_base;
    int *addr1;
    int *addr2;

    // Open /dev/mem device
    fd = open("/dev/mem", O_RDWR | O_SYNC);
    if (fd == -1) {
        perror("could not open /dev/mem\n");
        return 1;
    }

   
    hps_ddr_base = mmap(NULL, HPS_DDR_SPAN, PROT_READ | PROT_WRITE, MAP_SHARED, fd, HPS_DDR_BASE);
    h2f_base = mmap(NULL, 0x1000, PROT_READ | PROT_WRITE, MAP_SHARED, fd, HPS_AXI_BASE);
    
    if (hps_ddr_base == MAP_FAILED) {
        perror("could not mirror HPS DDR3 to user space\n");
        close(fd);
        return 1;
    }

    // Write 0xAA to 0x20000000
    addr1 = (int*)(hps_ddr_base + 0x20000000);
    *addr1 = 0xAA;

    // Write 0x1 to 0xC0000000
    addr2 = (int*)(h2f_base);
    *addr2 = 0x1;

    // Unmap and close the /dev/mem device
    munmap(hps_ddr_base, HPS_DDR_SPAN);
    close(fd);

    return 0;
}

Thank you again for your help. Please close this thread, Adzim.

Regards.

[AdzimZM_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.